Digital receiver for reactive radio

Abstract

A digital receiver is disclosed. In one aspect, the receiver includes a receiving module for receiving packetized data. The receive may further include a first processing module for packet detection having a first programmable processor. The receiver may further include a second processing module for demodulation and packet decoding having a second programmable processor. The receiver may further include a first digital receive controller having a third processor arranged for being notified of detection of data by the first processing module and for activating the second processing module.

1 . A digital receiver comprising:
 a receiving module for receiving packetized data;   a first processing module for packet detection comprising a first programmable processor;   a second processing module for demodulation and packet decoding comprising a second programmable processor;   a first digital receive controller comprising a third processor arranged for being notified of detection of data by the first processing module and for activating the second processing module.   
   
   
       2 . The digital receiver as in  claim 1 , wherein the receiving module for receiving packetized data is an analogue front end. 
   
   
       3 . The digital receiver as in  claim 1 , wherein, in use, the power consumption of the first processor is lower than the power consumption of the second processor. 
   
   
       4 . The digital receiver as in  claim 3 , wherein, in use, the power consumption of the first processing module is lower than the power consumption of the second processing module. 
   
   
       5 . The digital receiver as in  claim 1 , wherein the first processor is an application specific instruction set processor. 
   
   
       6 . The digital receiver as in  claim 1 , wherein the second processor is a general purpose processor. 
   
   
       7 . The digital receiver as in  claim 1 , wherein the first processing module comprises a third processing module for power level detection and a fourth processing module for synchronization, the fourth processing module comprising the first processor. 
   
   
       8 . The digital receiver as in  claim 7 , wherein the third processing module is arranged for being fed with packetized data from the receiving module for receiving packetized data. 
   
   
       9 . The digital receiver as in  claim 7 , wherein the third processing module is a hardware block. 
   
   
       10 . The digital receiver as in  claim 7 , further comprising a second controller for the first processing module, the second controller being arranged for receiving input from the third processing module and arranged for activating the fourth processing module. 
   
   
       11 . The digital receiver as in  claim 10 , wherein the fourth processing module is arranged for receiving control signals from the second controller. 
   
   
       12 . The digital receiver as in  claim 10 , wherein the second controller is a configurable hardware block. 
   
   
       13 . The digital receiver as in  claim 7 , wherein the third processing module is arranged for providing settings for the receiving module for receiving packetized data. 
   
   
       14 . The digital receiver as in  claim 1 , wherein the first processor is optimized for correlation. 
   
   
       15 . The digital receiver as in  claim 1 , the receiver comprising a plurality of the first processing modules. 
   
   
       16 . The digital receiver as in  claim 15 , wherein at least two of the plurality of the first processing modules are arranged for sharing a same bus interface. 
   
   
       17 . The digital receiver as in  claim 15 , wherein the plurality of first processing modules have a same architecture. 
   
   
       18 . The digital receiver as in  claim 15 , the receiver comprising a plurality of receiving modules for receiving packetized data. 
   
   
       19 . The digital receiver as in  claim 18 , wherein each receiving module for receiving packetized data is connected to a corresponding antenna. 
   
   
       20 . The digital receiver as in  claim 15 , the digital receiver being arranged for operating in different modes, each of the first processing modules being programmable for operating in one of the modes. 
   
   
       21 . The digital receiver as in  claim 15 , wherein all the first processing modules share the second controller. 
   
   
       22 . The digital receiver as in  claim 15 , wherein each of the first processing modules has its own second controller. 
   
   
       23 . The digital receiver as in  claim 7 , wherein the fourth processing module is arranged for filtering and further comprises a first memory for buffering data packets. 
   
   
       24 . The digital receiver as in  claim 23 , wherein the fourth processing module is arranged for performing the filtering operation on a configurable hardware block. 
   
   
       25 . The digital receiver as in  claim 23 , wherein the first memory is a circular data buffer. 
   
   
       26 . The digital receiver as in  claim 23 , further comprising a second memory for data reception, in parallel to the first memory. 
   
   
       27 . The digital receiver as in  claim 1 , further comprising a transfer module for data transfer between the first or the second memory on the one hand and memory of the second processor on the other hand. 
   
   
       28 . The digital receiver as in  claim 27 , wherein the transfer module for data transfer comprises a bus and a direct memory access. 
   
   
       29 . The digital receiver as in  claim 28 , wherein the bus is a shared bus. 
   
   
       30 . The digital receiver as in  claim 28 , the receiver comprising a plurality of buses. 
   
   
       31 . The digital receiver as in  claim 30 , the receiver comprising a plurality of direct memory accesses. 
   
   
       32 . The digital receiver as in  claim 1 , further comprising a FEC coder arranged for being fed with data from the second processing module, the FEC coder being arranged for being activated by the first digital receive controller. 
   
   
       33 . The digital receiver as in  claim 1 , the receiver being arranged for processing signals according to one or more of the following group of standards: IEEE802.11a, IEEE802.11n, 3GPP-LTE, and IEEE802.16e. 
   
   
       34 . Use of a mobile terminal comprising a digital receiver as in  claim 1 , for establishing a soft hand-over between two base stations of a wireless communication system. 
   
   
       35 . A digital receiver comprising:
 means for receiving packetized data;   means for packet detecting, the detecting means being programmable;   means for demodulating and packet decoding, the demodulating and decoding means being programmable; and   means for being notified of detection of data by the detecting means and for activating the second processing module.