Semiconductor device and fabricating method thereof

Abstract

A semiconductor device including a semiconductor substrate having first and second device regions. A first trench is formed in the first region and a second trench is formed in the second region. The first trench and the second trench have different widths and different depths. The first trench and the second trench define device isolation regions and active regions.

1 . A semiconductor device comprising:
 a semiconductor substrate having high and low voltage regions;   a first trench formed in the high voltage region;   a second trench formed in the low voltage region; and   a third trench formed below the first trench,   wherein said first trench and said third trench have different widths and different depths, and said first trench and said second trench define device isolation regions and active regions.   
   
   
       2 . The semiconductor device of  claim 1 , wherein the high voltage region includes a CMOS operated by high voltage and the low voltage region includes a CMOS operated by low voltage. 
   
   
       3 . The semiconductor device of  claim 1 , wherein the first trench and the third trench have stepped sidewalls. 
   
   
       4 . The semiconductor device of  claim 3 , wherein width of the first trench is wider than that of the third trench. 
   
   
       5 . The semiconductor device of  claim 4 , wherein the first trench is formed with a depth identical to the second trench. 
   
   
       6 . The semiconductor device of  claim 1 , wherein each trench is filled with dielectric material. 
   
   
       7 . The semiconductor device of  claim 6 , wherein the dielectric material is an oxide layer. 
   
   
       8 - 23 . (canceled) 
   
   
       24 . The semiconductor device of  claim 1 , further comprising
 first-conductivity-type wells formed to a depth selected to withstand high voltage in the high voltage region of the semiconductor substrate; and
 second-conductivity-type wells formed in the low voltage region. 
   
   
   
       25 . The semiconductor device of  claim 24 , wherein the depth of the third trench is greater than the depth of the first-conductivity-type wells. 
   
   
       26 . The semiconductor device of  claim 1 , wherein the third trench is formed deeper than the second trench. 
   
   
       27 . The semiconductor device of  claim 1 , wherein the high voltage region comprises an NMOS transistor region and PMOS transistor region, and the first and third trenches are formed between the NMOS and PMOS transistor regions. 
   
   
       28 . The semiconductor device of  claim 24 , wherein the second-conductivity-type wells are formed thinner and narrower than the first-conductivity-type wells.