US2009173956A1PendingUtilityA1

Contact for a semiconductor light emitting device

Assignee: PHILIPS LUMILEDS LIGHTING COPriority: Dec 14, 2007Filed: Dec 14, 2007Published: Jul 9, 2009
Est. expiryDec 14, 2027(~1.4 yrs left)· nominal 20-yr term from priority
H10H 20/8506H10H 20/835H10H 20/018
51
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

An AlGaInP light emitting device is formed as a thin, flip chip device. The device includes a semiconductor structure comprising an AlGaInP light emitting layer disposed between an n-type region and a p-type region. N- and p-contacts electrically connected to the n- and p-type regions are both formed on the same side of the semiconductor structure. The semiconductor structure is connected to the mount via the contacts. The growth substrate is removed from the semiconductor structure and the thick transparent substrate is omitted, such that the total thickness of semiconductor layers in the device is less than 15 μm in some embodiments, less than 10 μm in some embodiments. The top side of the semiconductor structure may be textured.

Claims

exact text as granted — not AI-modified
1 . A method comprising:
 growing a semiconductor structure comprising an AlGaInP light emitting layer disposed between an n-type region and a p-type region over a growth substrate;   forming n- and p-contacts electrically connected to the n- and p-type regions of the semiconductor structure, wherein the contacts are both disposed on a same side of the semiconductor structure and wherein at least one of the n- and p-contacts is reflective;   connecting the semiconductor structure to a mount; and   after connecting the semiconductor structure to the mount, removing the growth substrate.   
   
   
       2 . The method of  claim 1  wherein removing the growth substrate comprises etching the growth substrate with an etch that terminates on an etch stop layer disposed between the semiconductor structure and the growth substrate. 
   
   
       3 . The method of  claim 2  wherein the etch stop layer is one of AlGaAs, InGaP, and AlGaInP. 
   
   
       4 . The method of  claim 2  wherein:
 the etch stop layer is AlGaAs; and   a portion of the semiconductor structure in direct contact with the etch stop layer is AlGaInP.   
   
   
       5 . The method of  claim 1  wherein the n- and p-contacts are formed prior to connecting the semiconductor structure to the mount. 
   
   
       6 . The method of  claim 1  wherein:
 the n-contact comprises Au and Ge; and   the n-contact is in direct contact with an n-type III-P layer.   
   
   
       7 . The method of  claim 1  wherein:
 the semiconductor structure comprises a p-type contact layer disposed between the p-type region and the p-contact; and   at least a portion of the p-type contact layer is doped to a hole concentration of at least 5×10 18  cm −3 .   
   
   
       8 . The method of  claim 7  wherein p-type dopants are introduced into the p-type contact layer by one of introduction during growth of the p-type contact layer and diffusion from a vapor source after growth of the p-type contact layer. 
   
   
       9 . The method of  claim 7  further comprising etching away portions of the p-type contact layer prior to forming the contact. 
   
   
       10 . The method of  claim 9  further comprising disposing a dielectric between the p-contact and the p-type region in at least one region corresponding to an etched-away portion of the p-type contact layer. 
   
   
       11 . The method of  claim 7  further comprising forming a dielectric layer with openings over the p-type contact layer, wherein portions of the p-type contact layer doped to a hole concentration of at least 5×10 18  cm −3  are aligned with openings in the dielectric layer. 
   
   
       12 . The method of  claim 7  wherein growing a semiconductor structure comprises growing the p-type contact layer by metal organic chemical vapor deposition at a growth rate less than 5000 Å per hour. 
   
   
       13 . The method of  claim 7  wherein the p-type contact layer is one of GaP, AlGaInP, and InGaP. 
   
   
       14 . The method of  claim 1  wherein growing the semiconductor structure comprises:
 growing a p-type contact layer;   depositing a layer comprising a dopant over the p-type contact layer, wherein the layer comprising a dopant is one of metal and dielectric;   annealing the structure; and   removing the layer comprising a dopant.   
   
   
       15 . The method of  claim 14  further comprising depositing a dielectric layer with openings over the p-type contact layer, prior to depositing the layer comprising a dopant. 
   
   
       16 . The method of  claim 1  wherein growing a semiconductor structure comprises growing a semiconductor wafer, the method further comprising dicing the wafer into individual semiconductor structures prior to connecting the semiconductor structure to a mount. 
   
   
       17 . The method of  claim 1  wherein an interface between the p-contact and the p-type region is configured such that when the semiconductor structure is forward biased, carriers tunnel through the interface. 
   
   
       18 . A device comprising:
 a semiconductor structure comprising an AlGaInP light emitting layer disposed between an n-type region and a p-type region;   n- and p-contacts electrically connected to the n- and p-type regions, wherein the n- and p-contacts are both formed on a same side of the semiconductor structure and wherein at least one of the n- and p-contacts is reflective; and   a mount, wherein the semiconductor structure is connected to the mount via the contacts;   wherein a total thickness of semiconductor layers in the device is less than 15 μm and at least a portion of a top side of the semiconductor structure is textured.   
   
   
       19 . The device of  claim 18  wherein at least a portion of the top side of the semiconductor structure is one of randomly roughened, patterned, and patterned in a photonic crystal pattern. 
   
   
       20 . The device of  claim 18  further comprising a p-type contact layer disposed between the p-type region and the p-contact, wherein an interface between the p-type contact layer and the p-contact is configured such that when the device is forward biased, carriers tunnel through the interface. 
   
   
       21 . The device of  claim 18  further comprising a p-type contact layer disposed between the p-type region and the p-contact, wherein an interface between at least a portion of the p-type contact layer and the p-contact is reflective. 
   
   
       22 . The device of  claim 21  wherein the p-type contact layer is doped to a hole concentration of at least 5×10 18  cm −3 . 
   
   
       23 . The device of  claim 21  wherein:
 the p-type contact layer is one of GaP, AlGaInP, and InGaP; and   the p-contact comprises Ag.   
   
   
       24 . The device of  claim 21  further comprising a conductive oxide disposed between at least a portion of the p-type contact layer and the p-contact, wherein the conductive oxide is one of ITO and ZnO. 
   
   
       25 . The device of  claim 18  wherein all semiconductor layers in the device except any light emitting layers have a band gap greater than a band gap of at least one light emitting layer.

Join the waitlist — get patent alerts

Track US2009173956A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.