Semiconductor storage device, and data reading method

Abstract

A semiconductor storage device comprises of a memory cell connected to a plate line and a bit line, a potential shift circuit which is connected to a bit line, temporarily changes in output voltage corresponding to the voltage change of the bit line when a voltage is applied to the plate line, and then outputs a voltage before the application of the voltage to the plate line, a charge transfer circuit for transferring charge stored on the potential shift circuit corresponding to the temporary output voltage change of the potential shift circuit, and a charge accumulation circuit for generating a read voltage from a memory cell after accumulating the transferred charge.

1 . A semiconductor storage device, comprising:
 a memory cell connected to a plate line and a bit line; and   a potential shift circuit which is connected to the bit line, whose output voltage temporarily changes depending on a voltage change of the bit line when a voltage is applied to the plate line, and which outputs a voltage before application of the voltage to the plate line.   
   
   
       2 . The device according to  claim 1 , further comprising
 a charge transfer circuit which is connected to the potential shift circuit, and transfers charge stored on the potential shift circuit on a temporary change of an output voltage of the potential shift circuit depending on the voltage change of the bit line.   
   
   
       3 . The device according to  claim 2 , further comprising
 a charge accumulation circuit which is connected to the charge transfer circuit, accumulates charge transferred from the charge transfer circuit, and generates a read voltage from the memory cell.   
   
   
       4 . The device according to  claim 3 , further comprising
 a sense amplifier determining a logical value of data held in the memory cell depending on input of the read voltage generated by the charge accumulation circuit.   
   
   
       5 . The device according to  claim 4 , further comprising
 a bit line initialization circuit which is connected to the bit line, and initializes potential of the bit line before reading data from the memory cell connected to the bit line.   
   
   
       6 . The device according to  claim 5 , further comprising
 an inverse amplification circuit which is connected to the bit line, and controls a transfer capability of the charge transfer circuit depending on a voltage change of the bit line.   
   
   
       7 . The device according to  claim 6 , further comprising
 a charge accumulation circuit which is connected to the charge transfer circuit, accumulates charge transferred from the charge transfer circuit, and generates a read voltage from the memory cell.   
   
   
       8 . The device according to  claim 7 , further comprising
 a sense amplifier determining a logical value of data held in the memory cell depending on input of the read voltage generated by the charge accumulation circuit.   
   
   
       9 . The device according to  claim 6 , further comprising
 a bit line initialization circuit which is connected to the bit line, and initializes potential of the bit line before reading data from the memory cell connected to the bit line.   
   
   
       10 . A method for reading data from a memory cell connected to a plate line and a bit line, comprising:
 a potential shift circuit, which is connected to the bit line, outputting a voltage temporarily changing depending on a voltage change of the bit line when a voltage is applied to the plate line;   a charge transfer circuit, which is connected to the potential shift circuit, transferring charge stored on the potential shift circuit, and   a charge accumulation circuit, which is connected to the charge transfer circuit, accumulating the transferred charge and generates a read voltage from a memory cell.