High performance latches

Abstract

An integrated circuit includes at least one latch circuit ( 300 ). The latch circuit ( 300 ) includes a first stage comprising a latch node ( 311 ) positioned between a first pull up device ( 303 ) operable to receive a first data signal and a first pull down device ( 302 ) operative to receive second data signal. A second stage includes a second pull up device ( 323 ) and a second pull down device ( 322 ) having the latch node ( 311 ) therebetween, wherein at least one gate of the first pull up or first pull down device ( 302, 303 ) is directly coupled to a gate of the second pull up or second pull down device ( 322, 323 ). An output inverter ( 330 ) is coupled to the latch node ( 311 ).

1 . An integrated circuit, comprising:
 at least one latch circuit, said latch circuit comprising:   a first stage comprising a latch node positioned between a first pull up device operable to receive a first data signal and a first pull down device operative to receive second data signal;   a second stage comprising a second pull up device and a second pull down device having said latch node therebetween, wherein at least one gate of said first pull up or first pull down device is directly coupled to a gate of said second pull up or said second pull down device, and an output inverter coupled to said latch node.   
   
   
       2 . The integrated circuit of  claim 1 , wherein an output of said output inverter provides an output for said latch circuit. 
   
   
       3 . The integrated circuit of  claim 2 , further comprising hold circuitry coupled between said output of said latch circuit and said latch node operative to hold said output of said latch circuit. 
   
   
       4 . The integrated circuit of  claim 3 , wherein said hold circuitry comprises an inverter including a first and a second transistor having their gates directly coupled, said gates of said first and a second transistor coupled to said output of said latch circuit. 
   
   
       5 . The integrated circuit of  claim 4 , wherein said first and a second transistor both include a terminal directly coupled to said latch node, said first and a second transistor being positioned in a layout for said circuit at a top of a feedback stack. 
   
   
       6 . The integrated circuit of  claim 1 , wherein said first pull up device comprises a first PMOS device operative to receive said first data signal and first pull device comprise a first NMOS transistor operative to receive said second data signal and said second pull up device comprises a second PMOS transistor and said second pull down device comprises a second NMOS transistor, wherein a gate of said first PMOS transistor is directly coupled to a gate of said second NMOS transistor and a gate of said first NMOS transistor is directly coupled to a gate of said second PMOS transistor. 
   
   
       7 . The integrated circuit of  claim 6 , wherein said gate of said first PMOS transistor is directly coupled to said gate of said second NMOS transistor by a first polysilicon comprising line and said gate of said first NMOS transistor is directly coupled to said gate of said second PMOS transistor by a second polysilicon comprising line. 
   
   
       8 . The integrated circuit of  claim 6 , further comprising an input inverter in series with a gate of one of said first pull up or pull down devices. 
   
   
       9 . The integrated circuit of  claim 8 , wherein said input inverter is in series with a gate of said first PMOS transistor operable to provide said complement of said second data signal. 
   
   
       10 . The integrated circuit of  claim 9 , wherein an NMOS transistor of said input inverter is sized larger than a PMOS transistor of said input inverter. 
   
   
       11 . The integrated circuit of  claim 9 , wherein said at least one latch circuit comprises a first and a second of said latch circuit, said first and second latch circuits having said first and said second data signals swapped relative to said first NMOS transistor and said first PMOS transistor. 
   
   
       12 . The integrated circuit of  claim 9 , further comprising at least one dynamic logic gate having first and second dynamic nodes, wherein said first dynamic node is coupled to a gate of said first NMOS transistor and said second dynamic node is coupled to a gate of said first PMOS. 
   
   
       13 . The integrated circuit of  claim 6 , further comprising an input inverter in series with a gate of said first NMOS transistor operable to provide said complement of said first data signal. 
   
   
       14 . The integrated circuit of  claim 13 , wherein a PMOS of said input inverter is sized larger than a NMOS of said input inverter. 
   
   
       15 . The integrated circuit of  claim 13 , further comprising at least one dynamic logic gate having first and second dynamic nodes, wherein said first dynamic node is coupled to a gate of said first NMOS input transistor and said second dynamic node is coupled to a gate of said first PMOS transistor. 
   
   
       16 . The integrated circuit of  claim 6 , wherein (i) said first PMOS transistor and said second NMOS transistor and (ii) said first NMOS transistor and said second PMOS transistor are arranged in columns and have a straight polysilicon comprising gate geometry. 
   
   
       17 . The integrated circuit of  claim 6 , further comprising hold circuitry coupled between an output of said latch circuit and said latch node operative to hold said output of said latch circuit, wherein a layout of said integrated circuit comprises stacking transistors comprising said hold circuitry with said first and second NMOS transistors with gates driven from said output node of said latch circuit connected to said latch node. 
   
   
       18 . An integrated circuit comprising at least one RS latch circuit, said RS latch circuit comprising:
 a first stage comprising a latch node positioned between a first PMOS pull up device operative to receive said first data signal and a first NMOS pull down device operative to receive a second data signal;   a second stage comprising a second PMOS pull up device and a second NMOS pull down device, wherein a gate of said first PMOS device is directly coupled to a gate of said second NMOS device and a gate of said first NMOS device is directly coupled to a gate of said second PMOS device,   an output inverter coupled to said latch node, and   hold circuitry comprising a first and a second hold transistor having their gates directly coupled, said gates of said first and a second hold transistor coupled to an output of said clocked latch circuit operative to hold said output of said latch circuit.   
   
   
       19 . The integrated circuit of  claim 18 , wherein said at least one latch circuit comprises a first and a second of said latch circuit, said first and second latch circuits having said first and said second data signals swapped relative to said first NMOS pull down device and said first PMOS pull up device. 
   
   
       20 . The integrated circuit of  claim 18 , further comprising an input inverter in series with a gate of said first NMOS pull down device operable to provide said complement of said first data signal.