Array substrate, display device having the same and method of manufacturing the same

Abstract

An array substrate includes a switching element, a signal transmission line, a passivation layer and a pixel electrode. The switching element is disposed on an insulating substrate. The signal transmission line is connected to the switching element and includes a barrier layer, a conductive line, and a copper nitride layer. The barrier layer is disposed on the insulating substrate. The conductive line is disposed on the barrier layer and includes copper or copper alloy. The copper nitride layer covers the conductive line. The passivation layer covers the switching element and the signal transmission line and has a contact hole through which a drain electrode of the switching element is partially exposed. The pixel electrode is disposed on the insulating substrate, and is connected to the drain electrode of the switching element through the contact hole.

1 . A method for manufacturing an array substrate, comprising:
 forming a barrier layer on an insulating substrate;   forming a gate line comprising copper or copper alloy and a gate electrode connected to the gate line on the barrier layer;   applying nitride plasma on the gate line and the gate electrode;   depositing a gate insulating layer on the insulating substrate to cover the gate line and the gate electrode; and   forming a data line, a source electrode connected to the data line, a drain electrode spaced apart from the source electrode, and a semiconductor pattern on the gate insulating layer, the semiconductor pattern being on the gate electrode between the source electrode and the drain electrode.   
   
   
       2 . The method of  claim 1 , wherein the nitride plasma is applied in the same chamber in which the gate insulating layer is deposited, in situ. 
   
   
       3 . The method of  claim 2 , wherein the nitride plasma is applied at an electric power of no less than about 300 W for no less than about 20 seconds in an ammonia atmosphere. 
   
   
       4 . The method of  claim 2 , wherein depositing the gate insulating layer comprises:
 injecting a first gas mixture comprising silane gas, nitrogen gas, and ammonia gas into a chamber to form a first gate insulating layer on the insulating substrate, the amount of silane gas in the first gas mixture being no more than about 6.43% by volume;   injecting a second gas mixture comprising silane gas, nitrogen gas, and ammonia gas into the chamber to form a second gate insulating layer on the insulating substrate, the amount of silane gas in the second gas mixture being no less than about 6.43% by volume; and   injecting a third gas mixture comprising silane gas, nitrogen gas, and ammonia gas into the chamber to form a third gate insulating layer on the insulating substrate, the amount of silane gas in the third gas mixture being no more than about 6.43% by volume.   
   
   
       5 . The method of  claim 4 , wherein the thickness of the first gate insulating layer is no less than about 10 {acute over (Å)}. 
   
   
       6 . A method of manufacturing an array substrate, comprising:
 forming a gate line, a gate electrode connected to the gate line, and a gate insulating layer covering the gate line and the gate electrode on an insulating substrate;   forming a semiconductor pattern on the gate insulating layer corresponding to the gate electrode;   forming a data line comprising copper or copper alloy, a source electrode connected to the data line, and a drain electrode spaced apart from the source electrode with respect to the semiconductor pattern on the gate insulating layer;   applying nitride plasma on the data line, the source electrode, and the drain electrode; and   depositing a passivation layer on the gate insulating layer to cover the semiconductor pattern, the data line, the source electrode, and the drain electrode.   
   
   
       7 . The method of  claim 6 , further comprising:
 forming a conductive barrier layer on the gate insulating layer on which the semiconductor pattern is formed.   
   
   
       8 . The method of  claim 7 , wherein the conductive barrier layer comprises metal or alloy. 
   
   
       9 . The method of  claim 6 , wherein forming the semiconductor pattern on the gate insulating layer comprises:
 forming an amorphous silicon layer on the gate insulating layer; and   forming an n+ amorphous silicon layer on the amorphous silicon layer.   
   
   
       10 . The method of  claim 9 , further comprising:
 partially etching the n+ amorphous silicon layer by using the source electrode and the drain electrode treated by the nitride plasma as an etching mask.   
   
   
       11 . A method for manufacturing an array substrate, comprising:
 depositing a first barrier layer, a first conductive layer comprising copper or copper alloy, and a first copper nitride layer on an insulating substrate, in sequence;   patterning the first barrier layer, the first conductive layer, and the first copper nitride layer to form a gate line and a gate electrode connected to the gate line;   depositing a gate insulating layer on the insulating substrate to cover the gate line and the gate electrode; and   forming a data line, a source electrode connected to the data line, a drain electrode spaced apart from the source electrode, and a semiconductor pattern on the gate insulating layer, the semiconductor pattern being on the gate electrode between the source electrode and the drain electrode.   
   
   
       12 . The method of  claim 11 , wherein forming the data line, the source electrode, the drain electrode, and the semiconductor pattern comprises:
 depositing a second barrier layer, a second conductive layer comprising copper or copper alloy, and a second copper nitride layer on the gate insulating layer, in sequence; and   patterning the second barrier layer, the second conductive layer, and the second copper nitride layer.   
   
   
       13 . The method of  claim 12 , wherein forming the data line, the source electrode, the drain electrode, and the semiconductor pattern comprises:
 applying nitride plasma on the data line, the source electrode, and the drain electrode.   
   
   
       14 . A method for manufacturing an array substrate, comprising:
 forming a barrier layer on an insulating substrate;   forming a gate line comprising copper or copper alloy and a gate electrode connected to the gate line on the barrier layer;   applying hydrogen plasma on the gate line and the gate electrode;   injecting a first gas mixture comprising silane gas, nitrogen gas, and ammonia gas into a chamber to form a first gate insulating layer on the insulating substrate, the amount of silane gas in the first gas mixture being no more than about 6.43% by volume;   injecting a second gas mixture comprising silane gas, nitrogen gas and ammonia gas into the chamber to form a second gate insulating layer on the insulating substrate, the amount of silane gas in the second gas mixture being no less than about 6.43% by volume;   injecting a third gas mixture comprising silane gas, nitrogen gas and ammonia gas into the chamber to form a third gate insulating layer on the insulating substrate, the amount of silane gas in the third gas mixture being no more than about 6.43% by volume; and   forming a data line, a source electrode connected to the data line, a drain electrode spaced apart from the source electrode, and a semiconductor pattern on the third gate insulating layer, the semiconductor pattern being on the gate electrode between the source electrode and the drain electrode.