Semiconductor memory device having a plurality of chips and capability of outputting a busy signal

Abstract

One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.

1 . A semiconductor memory device comprising a plurality of memory chips in a package, wherein
 a first busy state takes effect when a power supply voltage reaches a specified value and an initialization operation starts in each of said plurality of memory chips after a power on sequence;   said first busy state is maintained until said initialization operation is completed in all of said plurality of memory chips; and   said first busy state is released after said initialization operation is completed in all of said plurality of memory chips.   
   
   
       2 - 27 . (canceled)