Integrated device technology using a buried power buss for major device and circuit advantages

Abstract

A method for providing an improved integrated circuit device is disclosed. The method comprises the steps of providing active and passive areas in the substrate, providing a plurality of slots in the substrate after providing the active and passive areas, and oxidizing the plurality of slots. The method further comprises providing metal in each of the plurality of slots, providing a dielectric coating over the slots, and providing etched contacts in select areas remote from the location of the slots. Additionally, the method provides an additional layer of metal that interconnects the contacts and the buried metal in select areas where contacts were etched, resulting in metal of three levels; and provides one level of the metal is surface and two levels of the metal that comprise a buried power buss (BPB).

1 . A method for providing an integrated circuit device comprising the steps of:
 providing a plurality of slots in the substrate;   providing dielectric coated metal in each of the plurality of slots;   providing etched contacts in areas remote from the location of the plurality of slots;   providing an additional layer of metal that interconnects the etched contacts and the metal in the slots resulting in a metal of three levels; and   providing one level of the metal on a top surface of the substrate and the other two levels of the metal comprise a buried power buss (BPB).   
   
   
       2 . The method of  claim 1  wherein the plurality of slots are oxidized. 
   
   
       3 . The method of  claim 1  wherein the providing steps comprising the step of providing three independent oxide isolated metal layers being of sufficient thickness to carry high current. 
   
   
       4 . The method of  claim 2  wherein select slots are opened in the substrate prior to metal to allow the oxide to be removed from the bottom of slots that are to make ground contact to the substrate and metal contact to the buried metal to replace a sinker. 
   
   
       5 . The method of  claim 1  wherein three layers of metal are provided with only one layer of metal requiring masking and pattern etching. 
   
   
       6 . The method of  claim 1  wherein the slots are located to minimize electro-migration. 
   
   
       7 . The method of  claim 1  wherein three layers of isolated metal interconnect are formed while only requiring one layer of dielectric to be deposited and contact etched. 
   
   
       8 . The method of  claim 2  wherein a high current is carried on the buried power buss (BPB) and the one layer is for interconnection of low power circuitry. 
   
   
       9 . An integrated circuit comprising:
 a substrate;   a plurality of slots in the substrate;   a dielectric coated metal in each of the plurality of slots;   a plurality of contacts in areas of the substrate remote from the slots; and   an additional layer of metal that interconnects the etched contacts and the metal in the slots, resulting in a metal of three levels, wherein one level of the metal is provided on a top surface of the substrate and the other two levels of metals comprise a buried power buss.   
   
   
       10 . The integrated circuit of  claim 9  wherein the three levels of the metal being of sufficient thickness to carry a high current. 
   
   
       11 . The integrated circuit of  claim 9 , wherein the high current is carried on the buried power loss and the one layer is for interconnection of low power circuitry.