High-k/metal gate stack using capping layer methods, ic and related transistors

Abstract

Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.

1 . A method comprising:
 providing an implanted substrate with a n-type metal oxide semiconductor (NMOS) region and a p-type metal oxide semiconductor (PMOS) region;   depositing a high dielectric constant (high-k) dielectric layer over the implanted substrate;   forming a first metal having a work function commensurate with a first one of the NMOS region and the PMOS region over the first one of the NMOS and the PMOS regions only, leaving the high-k dielectric layer exposed over a second one of the NMOS and PMOS regions;   depositing a second metal having a work function commensurate with the second one of the NMOS region and the PMOS region over the implanted substrate;   depositing a polysilicon over the implanted substrate; and   patterning to form a first gate stack over the NMOS region and a second gate stack over the PMOS region on the implanted substrate.   
   
   
       2 . The method of  claim 1 , further comprising depositing a capping layer over the implanted substrate prior to depositing the second metal. 
   
   
       3 . The method of  claim 2 , wherein the capping layer includes a dielectric. 
   
   
       4 . The method of  claim 3 , wherein the capping layer is selected from the group consisting of: lanthanum oxide (La 2 O 3 ), dysprosium oxide (DyO), yttrium oxide (Y 2 O 3 ), barium oxide (BaO), strontium oxide (SrO), scandium oxide (ScO), cerium oxide (CeO), praseodymium oxide (PrO), neodymium (NdO), gadolinium oxide (GdO), erbium oxide (ErO). 
   
   
       5 . The method of  claim 2 , wherein the capping layer includes a metal. 
   
   
       6 . The method of  claim 5 , wherein the capping layer is selected from the group consisting of: lanthanum (La), dysprosium (Dy), yttrium (Y), strontium (Sr), scandium (Sc), barium (Ba), cerium (Ce), praseodymium (Pr), neodymium (Nd), gadolinium (Gd), erbium (Er). 
   
   
       7 . The method of  claim 2 , wherein the high-k dielectric layer includes oxygen and the capping layer includes a rare earth metal that reacts with the high-k dielectric over the first one of the NMOS region and the PMOS region to form a dielectric, and remains metallic over the second one of the NMOS region and the PMOS region. 
   
   
       8 . The method of  claim 7 , wherein the capping layer is selected from the group consisting of: ytterbium (Yb), dysprosium (Dy), lanthanum (La), yttrium (Y), strontium (Sr), scandium (Sc), barium (Ba), cerium (Ce), praseodymium (Pr), neodymium (Nd), gadolinium (Gd) and erbium (Er). 
   
   
       9 . The method of  claim 1 , wherein the high-k dielectric layer is selected from the group consisting of: hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), hafnium silicon oxide (HfSiO x ), hafnium aluminum oxide (HfAlO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), yttrium oxide (Y 2 O 3 ), strontium oxide (SrO) and strontium titanium oxide (SrTiO). 
   
   
       10 . The method of  claim 1 , wherein the first one of the NMOS and PMOS region is the PMOS region, and the first metal is selected from the group consisting of: titanium nitride (TiN), ruthenium (Ru), tantalum nitride (TaN), tantalum carbide (TaC), titanium carbide (TiC), titanium oxy-nitride (TiON), rhenium (Re), tungsten (W), tantalum silicon nitride (TaSiN), iridium (Ir), nickel silicide (NiSi), iridium silicide (IrSi), niobium (Nb), vanadium (V) and aluminum (Al). 
   
   
       11 . The method of  claim 1 , wherein the second one of the NMOS and PMOS region is the NMOS region, and the second metal is selected from the group consisting of: titanium nitride (TiN), ruthenium (Ru), tantalum nitride (TaN), tantalum carbide (TaC), titanium carbide (TiC), titanium oxy-nitride (TiON), rhenium (Re), tungsten (W), tantalum silicon nitride (TaSiN), iridium (Ir), nickel silicide (NiSi), iridium silicide (IrSi), niobium (Nb), vanadium (V) and aluminum (Al). 
   
   
       12 . An integrated circuit comprising:
 a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen;   a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and   wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.   
   
   
       13 . The IC of  claim 12 , wherein the first dielectric layer is under the first metal in the gate electrode in the first type transistor. 
   
   
       14 . The IC of  claim 12 , wherein the second dielectric layer contacts the first dielectric layer in the second type transistor. 
   
   
       15 . The IC of  claim 12 , wherein the first type transistor includes an p-type field effect transistor (PFET) and the second type transistor includes a n-type field effect transistor (NFET). 
   
   
       16 . The IC of  claim 12 , wherein each gate electrode further includes a polysilicon portion. 
   
   
       17 . The IC of  claim 12 , wherein the second metal in the first type transistor and the second type transistor are electrically coupled. 
   
   
       18 . The IC of  claim 12 , wherein the rare earth metal is selected from the group consisting of: ytterbium (Yb), dysprosium (Dy), lanthanum (La), yttrium (Y), strontium (Sr), scandium (Sc), barium (Ba), cerium (Ce), praseodymium (Pr), neodymium (Nd), gadolinium (Gd) and erbium (Er). 
   
   
       19 . A transistor comprising:
 a gate stack including:
 a high dielectric constant (high-k) dielectric layer over a substrate, 
 a capping layer including an oxide of a rare earth metal over the high-k dielectric layer, 
 a metal over the oxide of the rare earth metal, the metal having a work function commensurate with a well in the substrate, and 
 a polysilicon over the metal. 
   
   
   
       20 . The transistor of  claim 19 , wherein the rare earth metal is selected from the group consisting of: ytterbium (Yb), dysprosium (Dy), lanthanum (La), yttrium (Y), strontium (Sr), scandium (Sc), barium (Ba), cerium (Ce), praseodymium (Pr), neodymium (Nd), gadolinium (Gd) and erbium (Er). 
   
   
       21 . The transistor of  claim 19 , wherein the high-k dielectric layer is selected from the group consisting of: hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), hafnium silicon oxide (HfSiO x ), hafnium aluminum oxide (HfAlO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), yttrium oxide (Y 2 O 3 ), strontium oxide (SrO) and strontium titanium oxide (SrTiO). 
   
   
       22 . A transistor comprising:
 a gate stack including:
 a high dielectric constant (high-k) dielectric layer over a substrate, the high-k dielectric layer including oxygen, 
 a first metal having a work function commensurate with a well in the substrate, 
 a capping layer including a rare earth metal over the first metal, 
 a second metal over the capping layer, the second metal having a work function incompatible with the well in the substrate, and 
 a polysilicon over the second metal. 
   
   
   
       23 . The transistor of  claim 22 , wherein the rare earth metal is selected from the group consisting of: ytterbium (Yb), dysprosium (Dy), lanthanum (La), yttrium (Y), strontium (Sr), scandium (Sc), barium (Ba), cerium (Ce), praseodymium (Pr), neodymium (Nd), gadolinium (Gd) and erbium (Er). 
   
   
       24 . The transistor of  claim 22 , wherein the high-k dielectric layer is selected from the group consisting of: hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), hafnium silicon oxide (HfSiO x ), hafnium aluminum oxide (HfAlO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), yttrium oxide (Y 2 O 3 ), strontium oxide (SrO) and strontium titanium oxide (SrTiO). 
   
   
       25 . The transistor of  claim 22 , wherein the well is a p-type well.