Printed circuit board having chip package mounted thereon and method of fabricating same

Abstract

Disclosed is a printed circuit board (PCB) and a method of fabricating the same. A contact portion is formed on an internal layer of the multi-layered PCB. A groove is formed so as to expose the contact portion of the internal layer. A chip package is mounted on the PCB while being flip-chip bonded to the exposed contact portion of the internal layer.

1 . A method of fabricating a printed circuit board having a chip package mounted thereon, comprising the steps of:
 laminating an insulating layer and a first circuit layer wherein a first circuit pattern is formed on an upper side of a second circuit layer on one side of a substrate;   removing portions of the insulating layer and the first circuit layer laminated on the substrate having a position corresponding to an area in which the chip package is mounted;   applying a photosensitive substance on internal and external layers so that the photosensitive substance adheres closely to the internal and external layers, and forming a second circuit pattern on the photosensitive substance to form an electric contact portion and to form a third circuit pattern on the external layer;   conducting an etching process using the second circuit pattern to form the third circuit pattern on the external layer and to form the electric contact portion on the internal layer; and   mounting the chip package wherein the chip package is connected to the electric contact portion formed on the exposed second circuit layer of the substrate.   
   
   
       2 . The method as set forth in  claim 1 , further comprising the steps of:
 applying a solder resistor on an outermost circuit layer and an exposed portion of the internal layer, and etching the electric contact portion to remove it; and   forming a conductive material on an area having a position corresponding to the removed electric contact portion, after the step of applying a second photosensitive substance.   
   
   
       3 . The method as set forth in  claim 1 , further comprising the step of connecting a side wall of the chip package through a lead frame to an external circuit layer after the step of mounting the chip package. 
   
   
       4 . A method of fabricating a printed circuit board having a chip package mounted thereon, comprising the steps of:
 forming a first circuit pattern, on a first circuit layer of a substrate having an electric contact portion to be connected to the chip package;   laminating an insulating layer and a second circuit layer on an upper side of the first circuit layer on one side of the substrate wherein the first circuit pattern is formed;   removing portions of the insulating layer and the second circuit layer, laminated on the substrate, having a position corresponding to an area wherein the chip package is to be mounted; and   mounting the chip package wherein the chip package is connected to the electric contact portion formed on the exposed first circuit layer of the substrate.   
   
   
       5 . The method as set forth in  claim 4 , further comprising the steps of:
 applying a solder resistor on an outermost circuit layer and an exposed portion of an internal layer, and etching the electric contact portion to remove it; and   forming a conductive material on an area having a position corresponding to the removed electric contact portion, after the step of removing portions of the insulating layer and the second circuit layer.   
   
   
       6 . The method as set forth in  claim 4 , further comprising the step of connecting a side wall of the chip package through a lead frame to an external circuit layer after the step of mounting the chip package. 
   
   
       7 . A method of fabricating a printed circuit board having a chip package mounted thereon, comprising the steps of:
 forming a first circuit pattern on a first circuit layer of a substrate having an electric contact portion connected to the chip package;   surrounding the electric contact portion with an etching resistor;   laminating an insulating layer and forming a hole wherein the chip package connected to the electric contact portion is mounted, and laminating a second circuit layer on the insulating layer;   laminating a photosensitive substance on the second circuit layer, forming a second circuit pattern on the photosensitive substance wherein a portion, having a position corresponding to the hole, is removed, and etching the resulting substrate to form a third circuit pattern on the second circuit layer; and   mounting the chip package wherein the chip package is connected to the electric contact portion formed on the exposed first circuit layer of the substrate.   
   
   
       8 . The method as set forth in  claim 7 , further comprising the steps of:
 applying a solder resistor on an outermost circuit layer and an exposed portion of an internal layer, and etching the electric contact portion to remove it; and   forming a conductive material on an area which has a position corresponding to the removed electric contact portion, after the step of laminating a photosensitive substance on the second circuit layer.   
   
   
       9 . The method as set forth in  claim 7 , further comprising the step of connecting a side wall of the chip package through a lead frame to an external circuit layer after the step of mounting the chip package.