Computer-Based Method and System for Simulating Static Timing Clocking Results

Abstract

A method, system and computer-readable medium are presented for creating unique clock waveform checking commands for an event simulator to validate that the logical creation matches the timing definitions. The method includes selecting one or more clock signals for validation; specifying timing definitions of the selected clock signals; automatically categorizing the selected clock signals based on their synchrony; automatically matching each selected clock signal to a corresponding clock cycle by parsing the specified timing definitions; specifying one or more test cases for an event simulator, wherein the test cases simulate logic for generating each selected clock signal; validating that the logic for generating each selected clock signal matches the specified timing definitions for each selected clock signal.

1 . A computer-based method for validating clock signals in an integrated circuit comprising:
 selecting one or more clock signals for validation;   specifying timing definitions of the selected clock signals;   automatically categorizing the selected clock signals based on their synchrony;   automatically matching each selected clock signal to a corresponding clock cycle by parsing the specified timing definitions;   specifying one or more test cases for an event simulator, wherein the test cases simulate logic for generating each selected clock signal; and   validating that the logic for generating each selected clock signal matches the specified timing definitions for each selected clock signal.   
   
   
       2 . The method of  claim 1 , wherein said validating further comprises:
 reading said one or more test cases into the event simulator;   executing said one or more test cases with the event simulator;   comparing a simulated waveform for each selected clock signal to the timing definitions for the selected clock signal;   determining whether the simulated waveform for each selected clock signal matches the timing definitions for the clock signal; and   in response to determining that the simulated waveform does not match the timing definitions, reporting an error to the user.   
   
   
       3 . The method of  claim 1 , wherein the event simulator is capable of executing test cases encoded in a Tool Command Language (Tcl). 
   
   
       4 . The method of  claim 1 , wherein said selecting further comprises excluding clock signals listed in an ignore file. 
   
   
       5 . The method of  claim 1 , wherein said automatically matching further comprises:
 determining a phase for each selected clock signal based on the specified timing definitions; and   mapping the phase to a primary input and a primary output of each selected clock signal.   
   
   
       6 . The method of  claim 1 , wherein said timing definitions are imported from a static timing tool. 
   
   
       7 . The method of  claim 1 , wherein said timing definitions include:
 a pulse width;   a cycle time; and   an alignment to other synchronous clock signals.   
   
   
       8 . A system for validating clock signals in an integrated circuit comprising:
 a processor;   a memory;   means for selecting one or more clock signals for validation;   means for specifying timing definitions of the selected clock signals;   automatically categorizing the selected clock signals based on their synchrony;   means for automatically matching each selected clock signal to a corresponding clock cycle by parsing the specified timing definitions;   means for specifying one or more test cases for an event simulator, wherein the test cases simulate logic for generating each selected clock signal; and   means for validating that the logic for generating each selected clock signal matches the specified timing definitions for each selected clock signal.   
   
   
       9 . The system of  claim 8 , wherein said means for validating further comprises:
 means for reading said one or more test cases into the event simulator;   means for executing said one or more test cases with the event simulator;   means for comparing a simulated waveform for each selected clock signal to the timing definitions for the selected clock signal;   means for determining whether the simulated waveform for each selected clock signal matches the timing definitions for the clock signal; and   means, responsive to determining that the simulated waveform does not match the timing definitions, for reporting an error to the user.   
   
   
       10 . The system of  claim 8 , wherein the event simulator is capable of executing test cases encoded in a Tool Command Language (Tcl). 
   
   
       11 . The system of  claim 8 , wherein said means for selecting further comprises means for excluding clock signals listed in an ignore file. 
   
   
       12 . The system of  claim 8 , wherein said means for automatically matching further comprises:
 means for determining a phase for each selected clock signal based on the specified timing definitions; and   means for mapping the phase to a primary input and a primary output of each selected clock signal.   
   
   
       13 . The system of  claim 8 , wherein said timing definitions are imported from a static timing tool. 
   
   
       14 . The system of  claim 8 , wherein said timing definitions include:
 a pulse width;   a cycle time; and   an alignment to other synchronous clock signals.   
   
   
       15 . A computer-readable medium for validating clock signals in an integrated circuit, said computer-readable medium encoded with a computer program that, when executed causes a data processing system to perform the steps of:
 selecting one or more clock signals for validation;   specifying timing definitions of the selected clock signals;   automatically categorizing the selected clock signals based on their synchrony;   automatically matching each selected clock signal to a corresponding clock cycle by parsing the specified timing definitions;   specifying one or more test cases for an event simulator, wherein the test cases simulate logic for generating each selected clock signal; and   validating that the logic for generating each selected clock signal matches the specified timing definitions for each selected clock signal.   
   
   
       16 . The computer-readable medium of  claim 15 , wherein said validating further comprises:
 reading said one or more test cases into the event simulator;   executing said one or more test cases with the event simulator;   comparing a simulated waveform for each selected clock signal to the timing definitions for the selected clock signal;   determining whether the simulated waveform for each selected clock signal matches the timing definitions for the clock signal; and   in response to determining that the simulated waveform does not match the timing definitions, reporting an error to the user.   
   
   
       17 . The computer-readable medium of  claim 15 , wherein the event simulator is capable of executing test cases encoded in a Tool Command Language (Tcl). 
   
   
       18 . The computer-readable medium of  claim 15 , wherein said automatically matching further comprises:
 determining a phase for each selected clock signal based on the specified timing definitions; and   mapping the phase to a primary input and a primary output of each selected clock signal.   
   
   
       19 . The computer-readable medium of  claim 15 , wherein said timing definitions are imported from a static timing tool. 
   
   
       20 . The computer-readable medium of  claim 15 , wherein said timing definitions include:
 a pulse width;   a cycle time; and   an alignment to other synchronous clock signals.