Manufacturing method of multi-level non-volatile memory

Abstract

A manufacturing method of a multi-level non-volatile memory includes following steps. First, a tunneling dielectric layer and a charge storage layer are sequentially formed on the substrate. At least two stacked layers are formed on the charge storage layer. Every two stacked layers include an inter-gate dielectric layer, a control gate, and a cap layer in sequence. Next, the charge storage layer between the two stacked layers is removed to form a first trench. After spacers are formed at the sidewalls of the two stacked layers and of the first trench, the charge storage layer outside the two stacked layers is removed. Thereafter, a dielectric layer is formed on the substrate. An assist gate is formed between the two stacked layers and a select gate is respectively formed on the sidewalls outside the two stacked layers. A doped region is then formed in the substrate outside the two stacked layers.

1 . A manufacturing method of a multi-level non-volatile memory, comprising:
 forming a tunneling dielectric layer and a charge storage layer on a substrate, sequentially;   forming at least two stacked layers on the charge storage layer, wherein every two stacked layers comprise an inter-gate dielectric layer, a control gate, and a cap layer in sequence;   removing the charge storage layer between the two stacked layers to form a first trench;   forming spacers at the sidewalls of the two stacked layers and at the sidewalls of the first trench;   removing the charge storage layer lying outside the two stacked layers by using the spacers as a mask;   forming a dielectric layer on the substrate;   forming an assist gate between the two stacked layers, and forming two select gates and each respectively on the sidewalls outside the two stacked layers; and   forming two doped regions and each respectively in the substrate outside the two stacked layers, the select gate being located between the stacked layer and the doped region.   
   
   
       2 . The manufacturing method as claimed in  claim 1 , wherein the dielectric layer comprises high temperature thermal oxide layer. 
   
   
       3 . The manufacturing method as claimed in  claim 1 , wherein a thickness of the dielectric layer is between 100 A and 200 A. 
   
   
       4 . The manufacturing method as claimed in  claim 1 , wherein the step of forming the assist gate between the two stacked layers and respectively forming the select gate on the sidewalls outside the two stacked layers comprises:
 forming a conductive material layer on the substrate to fill the first trench; and   performing an etch back process to remove a portion of the conductive material layer until the cap layer is exposed.   
   
   
       5 . The manufacturing method as claimed in  claim 1 , wherein the material of the tunneling dielectric layer comprises silicon oxide. 
   
   
       6 . The manufacturing method as claimed in  claim 1 , wherein the tunneling dielectric layer is formed by performing a thermal oxidation process. 
   
   
       7 . The manufacturing method as claimed in  claim 1 , wherein the material of the inter-gate dielectric layer comprises silicon oxide/silicon nitride/silicon oxide. 
   
   
       8 . The manufacturing method as claimed in  claim 1 , wherein the material of the charge storage layer comprises doped polysilicon.