Wafer Carrying Apparatus

Abstract

A wafer carrying apparatus or cassette is disclosed, which includes a binding or retention unit, so as to prevent wafers from being damaged by crash, inadvertent egress or exiting, and so on. The wafer carrying apparatus includes a main body provided with a plurality of wafer insertion grooves formed on inner sides and an opening formed on a front surface to take wafers in and out, a binding unit configured to move up and down on the front surface of the main body, its position relative to the insertion grooves being variable so as to close and open the insertion grooves, and a mechanism for varying the position of the binding unit relative to the insertion grooves, the mechanism being connected to the binding unit.

1 . A method of manufacturing a plurality of wafers, comprising the steps of:
 removing a wafer cassette having said wafers therein from a first wafer processing apparatus;   transporting said wafer cassette to a second wafer processing apparatus;   when said wafers are at risk for inadvertent egress, securing said wafers within said wafer cassette using a wafer retention unit; and   placing said wafer cassette in said second wafer processing apparatus.   
   
   
       2 . The method of  claim 1 , wherein at least one of said first and second wafer processing apparatus performs at least one CMOS processing step. 
   
   
       3 . The method of  claim 1 , wherein the step of securing said wafer includes deflecting a wafer retention mechanism coupled to said wafer retention unit. 
   
   
       4 . The method of  claim 3 , wherein the step of removing said wafer cassette includes grasping a wafer cassette handle, said wafer cassette mechanism being configured to be grasped along with said wafer retention handle. 
   
   
       5 . The method of  claim 1 , wherein the step of placing said wafer cassette into said second wafer processing apparatus includes releasing a wafer retention mechanism handle such that the wafer is accessible by said equipment. 
   
   
       6 . The method of  claim 1 , wherein said at least one wafer retention unit is attached to an access side of said wafer cassette. 
   
   
       7 . The method of  claim 3 , wherein said wafer retention mechanism further includes an end of a spring attached to a bottom of said wafer retention unit. 
   
   
       8 . The method of  claim 7 , wherein an opposite end of said spring is attached to a bottom of said wafer cassette. 
   
   
       9 . The method of  claim 7 , wherein said spring is configured to enable the movement of said wafer retention unit when said wafer retention mechanism is deflected. 
   
   
       10 . The method of  claim 7 , wherein said spring is configured to maintain said wafer retention unit to a position substantially aligned with the grooves of said wafer protrusions when said wafer retention mechanism is not deflected. 
   
   
       11 . The method of  claim 3 , wherein the step of securing said wafer includes moving said at least one wafer retention unit to be offset from wafer insertion grooves. 
   
   
       12 . The method of  claim 3 , wherein deflecting said wafer retention mechanism further includes blocking an opening of the wafer insertion grooves to secure said wafer. 
   
   
       13 . The method of  claim 1 , wherein the step of placing said wafer cassette into said second wafer processing apparatus further includes unblocking the opening of the wafer insertion grooves to allow access by said equipment. 
   
   
       14 . The method of  claim 1 , wherein the step of securing said wafers comprises moving a plurality of wafer retention units to a position substantially offset with a plurality of said wafer protrusions. 
   
   
       15 . The method of  claim 14 , wherein said wafer retention mechanism is coupled to said plurality of wafer retention units. 
   
   
       16 . The method of  claim 15 , wherein the step of placing said wafer cassette into said second wafer processing apparatus comprises moving said plurality of wafer retention units to substantially align with said plurality of wafer protrusions. 
   
   
       17 . The method of  claim 1 , further comprising the step of performing a first CMOS processing operation in said first wafer processing apparatus and performing a second CMOS processing operation in said second wafer processing apparatus.