Voltage Controlled Static Random Access Memory

Abstract

A static random access memory (SRAM) comprising a plurality of SRAM cells, a plurality of wordlines (WL 0 -WLN) and a voltage regulator for driving the wordlines with a wordline voltage signal (VWLP). The wordline voltage signal is determined so as to reduce the likelihood of occurrence of read-disturbances and other memory instabilities. In one embodiment, the wordline voltage signal is determined as a function of the metastability voltage (VMETA) of the SRAM cells and an adjusted most positive down level voltage (VAMPDL) that is a function of a predetermined voltage margin (VM) and a most positive down level voltage (VMPDL) that corresponds to the read-disturb voltage of the SRAM cells.

1 . An integrated circuit, comprising:
 a static random access memory (SRAM) powered by an SRAM voltage signal having a first voltage, said SRAM including a plurality of wordlines; and   at least one wordline voltage regulator operatively configured to drive said plurality of wordlines with a wordline voltage signal having a second voltage lower than the first voltage;   wherein:
 said at least one voltage regulator includes a metastability voltage generator; and 
 said SRAM includes a plurality of SRAM cells each having a pair of internal voltage nodes and said metastability voltage generator comprises one of said plurality of SRAM cells having said pair of internal voltage nodes electrically coupled to one another. 
   
   
   
       2 . An integrated circuit according to  claim 1 , wherein each of said plurality of SRAM cells includes at least one input/output (I/O) device and at least one pull-down device electrically coupled to said I/O device, said I/O and pull-down devices including corresponding respective diffusion regions having identical as-designed widths. 
   
   
       3 . An integrated circuit according to  claim 2 , wherein each of said plurality of SRAM cells is a six-device SRAM cell. 
   
   
       4 . An integrated circuit according to  claim 1 , wherein said at least one voltage regulator includes a read-disturb generator. 
   
   
       5 . An integrated circuit according to  claim 4 , wherein said read-disturb voltage generator mimics at least one-half of each SRAM cell of said plurality of SRAM cells. 
   
   
       6 . An integrated circuit according to  claim 4 , wherein said read-disturb voltage generator comprises a variable current supply. 
   
   
       7 . An integrated circuit according to  claim 1 , wherein each of said plurality of SRAM cells has a metastability voltage, said at least one voltage regulator operatively configured to generate said second voltage as a function of said metastability voltage. 
   
   
       8 . An integrated circuit according to  claim 1 , wherein each of said plurality of SRAM cells has a most positive down level voltage that is a function of said second voltage, said at least one voltage regulator operatively configured to generate said second voltage as a function of said most positive down level voltage. 
   
   
       9 . An integrated circuit according to  claim 1 , wherein each of said plurality of SRAM cells has a metastability voltage and a most positive down level voltage that is a function of said second voltage, said voltage regulator operatively configured to generate said second voltage as a function of said metastability voltage and said most positive down level voltage. 
   
   
       10 . An integrated circuit according to  claim 1 , wherein said voltage regulator includes a feedback loop that feeds back said second voltage. 
   
   
       11 . An integrated circuit, comprising:
 a static random access memory (SRAM) powered by an SRAM voltage signal having a first voltage, said SRAM including a plurality of wordlines; and   at least one wordline voltage regulator operatively configured to drive said plurality of wordlines with a wordline voltage signal having a second voltage lower than the first voltage;   wherein said SRAM includes a plurality of SRAM cells each having a most positive down level voltage that is a function of said second voltage, said at least one voltage regulator operatively configured to generate said second voltage as a function of said most positive down level voltage.   
   
   
       12 . An integrated circuit, comprising:
 a static random access memory (SRAM) powered by an SRAM voltage signal having a first voltage, said SRAM including a plurality of wordlines; and   at least one wordline voltage regulator operatively configured to drive said plurality of wordlines with a wordline voltage signal having a second voltage lower than the first voltage;   wherein said SRAM includes a plurality of SRAM cells each having a metastability voltage and a most positive down level voltage that is a function of said second voltage, said voltage regulator operatively configured to generate said second voltage as a function of said metastability voltage and said most positive down level voltage.   
   
   
       13 . A method of powering a static random access memory (SRAM) that includes a plurality of SRAM cells and a plurality of wordlines, the method comprising:
 generating a metastability voltage;   generating a read-disturb voltage;   generating a wordline voltage as a function of the metastability voltage and the read-disturb voltage; and   driving the plurality of wordlines with the wordline voltage.   
   
   
       14 . A method according to  claim 13 , wherein each of the plurality of SRAM cells has an operation and said generating of the metastability voltage includes mimicking the operation. 
   
   
       15 . A method according to  claim 14 , wherein each of the plurality of SRAM cells has two mirror-image sides and said mimicking of the operation of each of the plurality of SRAM includes mimicking the operation in a cell having the two mirror-image sides electrically coupled together. 
   
   
       16 . A method according to  claim 15 , wherein said mimicking of the operation includes mimicking the operation in a cell having the two mirror-image sides electrically coupled together with a resistor. 
   
   
       17 . A method according to  claim 13 , wherein said generating of a read-disturb voltage includes generating the read-disturb voltage as a function of the wordline voltage. 
   
   
       18 . A method according to  claim 17 , wherein each of the plurality of SRAM cells has two mirror-image sides said generating of the read-disturb voltage includes driving at least one side of the two mirror-image sides with the wordline voltage. 
   
   
       19 . A method according to  claim 13 , wherein said driving of the plurality of wordlines includes driving the plurality of wordlines with the wordline voltage substantially only during a read cycle. 
   
   
       20 . A method according to  claim 13 , further comprising powering the plurality of wordlines with the wordline voltage substantially only during read cycles and with a power supply voltage at times other than the read cycles.