Layout for dut arrays used in semiconductor wafer testing

Abstract

A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set.

1 . A layout for devices under test formed on a semiconductor wafer for use in wafer testing, the layout comprising:
 a first array of devices under test;   a first pad set formed adjacent to the first array, the first pad set including a gate force pad, a source pad, and a drain pad, wherein each of the devices under test in the first array is connected in parallel to the drain pad of the first pad set;   a source tree routing structure connected to a source of each device under test in the first array, wherein the source tree connects the devices under test in the first array in parallel to the source pad, and wherein the source tree routing structure comprises:
 a first hierarchy of branches, each branch of the first hierarchy having a pair of segments connected to sources of two devices under test in the first array, wherein the pair of segments is electrically balanced; and 
 a second hierarchy of branches, each branch of the second hierarchy having a pair of segments connected to two branches of the first hierarchy; and 
   a selection circuit connected to each of the devices under test in the first array and the gate force pad, wherein the selection circuit is configured to selectively connect each of the devices under test in the first array to the gate force pad.   
   
   
       2 . The layout of  claim 1 , wherein the source tree routing structure comprises:
 a first branch at the first hierarchy of the source tree routing structure, wherein the first branch includes a first segment connected to the source of a first device under test and a second segment connected to the source of a second device under test, and wherein the first device under test is adjacent to the second device under test.   
   
   
       3 . The layout of  claim 2 , wherein the drain tree routing structure comprises:
 a second branch at the first hierarchy of the source tree routing structure, wherein the second branch includes a first segment connected to the source of a third device under test and a second segment connected to the source of a fourth device under test, wherein the third device under test is adjacent to the fourth device under test.   
   
   
       4 . The layout of  claim 3 , wherein the drain tree routing structure comprises:
 a third branch at the second hierarchy of the source tree routing structure, wherein the third branch includes first segment connected to the first branch and a second segment connected to the second branch, wherein the first branch is adjacent to the second branch, and wherein the first and second segments of the third branch are electrically balanced.   
   
   
       5 . The layout of  claim 4 , wherein the first, second, third, and fourth devices under test are disposed within a row of the first array. 
   
   
       6 . The layout of  claim 1 , wherein a device under test in the first array is formed within a cell, and further comprising:
 an L-shaped routing structure disposed at a corner of the cell, wherein the L-shaped routing structure is connected to the source and one of the segments of a branch of the first hierarchy of the source tree routing structure.   
   
   
       7 . The layout of  claim 1 , further comprising:
 a drain tree routing structure connected to a drain of each device under test in the first array, wherein the drain tree connects the devices under test in the first array in parallel to the drain pad, and wherein the drain tree routing structure comprises:
 a first hierarchy of branches, each branch of the first hierarchy having a pair of segments connected to drains of two devices under test in the first array, wherein the pair of segments is electrically balanced; and 
 a second hierarchy of branches, each branch of the second hierarchy having a pair of segments connected to two branches of the first hierarchy; and 
   
   
   
       8 . The layout of  claim 7 , wherein the drain tree routing structure comprises:
 a first branch at the first hierarchy of the drain tree routing structure, wherein the first branch includes a first segment connected to the drain of the first device under test and a second segment connected to the drain of the second device under test;   a second branch at the first hierarchy of the drain tree routing structure, wherein the second branch includes a first segment connected to the drain of the third device under test and the second segment connected to the drain of a fourth device under test; and   a third branch at a second hierarchy of the drain tree routing structure, wherein the third branch includes first segment connected to the first branch and a second segment connected to the second branch, wherein the first branch is adjacent to the second branch, and wherein the first and second segments of the third branch are electrically balanced.   
   
   
       9 . The layout of  claim 8 , wherein the first, second, third, and fourth devices under test are disposed within a row of the first array. 
   
   
       10 . The layout of  claim 7 , wherein a device under test in the first array is formed within a cell, and further comprising:
 a first L-shaped routing structure disposed at a first corner of the cell, wherein the first L-shaped routing structure is connected to the source of the device under test and one of the segments of a branch of the first hierarchy of the source tree routing structure; and   a second L-shaped routing structure disposed at a second corner of the cell, wherein the second L-shaped routing structure is connected to the drain of the device under test and one of the segments of a branch of the first hierarchy of the drain tree routing structure.   
   
   
       11 . A layout for devices under test formed on a semiconductor wafer for use in wafer testing, the layout comprising:
 a first array of devices under test;   a first pad set formed adjacent to the first array, the first pad set including a gate force pad, a source pad, and a drain pad, wherein each of the devices under test in the first array is connected in parallel to the source pad of the first pad set;   a drain tree routing structure connected to a drain of each device under test in the first array, wherein the drain tree connects the devices under test in the first array in parallel to the drain pad, and wherein the drain tree routing structure comprises:
 a first hierarchy of branches, each branch of the first hierarchy having a pair of segments connected to drains of two devices under test in the first array, wherein the pair of segments is electrically balanced; and 
 a second hierarchy of branches, each branch of the second hierarchy having a pair of segments connected to two branches of the first hierarchy; and 
   a selection circuit connected to each of the devices under test in the first array and the gate force pad, wherein the selection circuit is configured to selectively connect each of the devices under test in the first array to the gate force pad.   
   
   
       12 . The layout of  claim 11 , wherein the drain tree routing structure comprises:
 a first branch at the first hierarchy of the drain tree routing structure, wherein the first branch includes a first segment connected to the drain of a first device under test and a second segment connected to the drain of a second device under test, and wherein the first device under test is adjacent to the second device under test.   
   
   
       13 . The layout of  claim 12 , wherein the drain tree routing structure comprises:
 a second branch at the first hierarchy of the drain tree routing structure, wherein the second branch includes a first segment connected to the drain of a third device under test and a second segment connected to the drain of a fourth device under test, wherein the third device under test is adjacent to the fourth device under test.   
   
   
       14 . The layout of  claim 13 , wherein the drain tree routing structure comprises:
 a third branch at the second hierarchy of the drain tree routing structure, wherein the third branch includes first segment connected to the first branch and a second segment connected to the second branch, wherein the first branch is adjacent to the second branch, and wherein the first and second segments of the third branch are electrically balanced.   
   
   
       15 . The layout of  claim 14 , wherein the first, second, third, and fourth devices under test are disposed within a row of the first array. 
   
   
       16 . The layout of  claim 11 , wherein a device under test in the first array is formed within a cell, and further comprising:
 an L-shaped routing structure disposed at a corner of the cell, wherein the L-shaped routing structure is connected to the drain and one of the segments of a branch of the first hierarchy of the drain tree routing structure.   
   
   
       17 . A method of forming a layout for devices under test formed on a semiconductor wafer for use in wafer testing, the method comprising:
 forming a first array of devices under test;   forming a first pad set formed adjacent to the first array, the first pad set including a gate force pad, a source pad, and a drain pad, wherein each of the devices under test in the first array is connected in parallel to the drain pad of the first pad set;   forming a source tree routing structure connected to a source of each device under test in the first array, wherein the source tree connects the devices under test in the first array in parallel to the source pad, and wherein the source tree routing structure comprises:
 a first hierarchy of branches, each branch of the first hierarchy having a pair of segments connected to sources of two devices under test in the first array, wherein the pair of segments is electrically balanced; and 
 a second hierarchy of branches, each branch of the second hierarchy having a pair of segments connected to two branches of the first hierarchy; and 
   forming a selection circuit connected to each of the devices under test in the first array and the gate force pad, wherein the selection circuit is configured to selectively connect each of the devices under test in the first array to the gate force pad.   
   
   
       18 . A method of forming a layout for devices under test formed on a semiconductor wafer for use in wafer testing, the method comprising:
 forming a first array of devices under test;   forming a first pad set formed adjacent to the first array, the first pad set including a gate force pad, a source pad, and a drain pad, wherein each of the devices under test in the first array is connected in parallel to the source pad of the first pad set;   forming a drain tree routing structure connected to a drain of each device under test in the first array, wherein the drain tree connects the devices under test in the first array in parallel to the drain pad, and wherein the drain tree routing structure comprises:
 a first hierarchy of branches, each branch of the first hierarchy having a pair of segments connected to drains of two devices under test in the first array, wherein the pair of segments is electrically balanced; and 
 a second hierarchy of branches, each branch of the second hierarchy having a pair of segments connected to two branches of the first hierarchy; and 
   forming a selection circuit connected to each of the devices under test in the first array and the gate force pad, wherein the selection circuit is configured to selectively connect each of the devices under test in the first array to the gate force pad.