Method of manufacturing a chip and a chip stack

Abstract

Provided are a chip, a chip stack, and a method of manufacturing the Same. A plurality of chips which each include: at least one pad formed on a wafer; and a metal layer which protrudes up to a predetermined thickness from the bottom of the wafer and is formed in a via hole exposing the bottom of the pad are stacked such that the pad and the metal layer of adjacent chips are bonded. This leads to a simplified manufacturing process, high chip performance and a small footprint for a chip stack.

1 . A chip, comprising:
 at least one pad formed on a wafer; and   a metal layer formed to protrude up to a predetermined thickness from the bottom of the wafer in a via hole penetrating the wafer to expose the bottom of the pad.   
   
   
       2 . The chip of  claim 1 , wherein the via hole has an aspect ratio of 1 to 3. 
   
   
       3 . The chip of  claim 1 , wherein the metal layer includes a first metal layer formed to a predetermined thickness from the exposed bottom of the pad using a copper and a second metal layer formed on the first metal layer to protrude up to a predetermined thickness from the bottom of the wafer using one of stannum/copper (Sn/Cu), stannum (Sn) and stannum/bismuth (Sn/Bi). 
   
   
       4 . A chip stack, comprising:
 a plurality of chips which include at least one pad formed on a wafer and a metal layer formed to protrude Up to a predetermined thickness from the bottom of the wafer in a via hole penetrating the wafer to expose the bottom of the pad,   wherein the pad and the metal layer of adjacent chips are bonded to each other.