Techniques for low-temperature ion implantation

Abstract

Techniques for low-temperature ion implantation are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for low-temperature ion implantation. The apparatus may comprise a wafer support mechanism to hold a wafer during ion implantation and to facilitate movement of the wafer in at least one dimension. The apparatus may also comprise a cooling mechanism coupled to the wafer support mechanism. The cooling mechanism may comprise a refrigeration unit, a closed loop of rigid pipes to circulate at least one coolant from the refrigeration unit to the wafer support mechanism, and one or more rotary bearings to couple the rigid pipes to accommodate the movement of the wafer in the at least one dimension.

1 . A wafer support mechanism comprising:
 a base and a first layer fabricated of a single piece of ceramic, said first layer disposed on said base, said base and said first layer defining at least one channel;   a plurality of electrodes disposed on said first layer; and   a second layer disposed on said plurality of electrodes.   
   
   
       2 . The wafer support mechanism of  claim 1 , wherein said ceramic is alumina. 
   
   
       3 . The wafer support mechanism of  claim 1 , wherein said first layer is an insulating layer. 
   
   
       4 . The wafer support mechanism of  claim 1 , wherein said base has a circumferential edge and said first layer is only disposed on said circumferential edge of said base. 
   
   
       5 . The wafer support mechanism of  claim 1 , wherein said first layer has a center region and said plurality of electrodes are disposed on said center region of said first layer. 
   
   
       6 . The wafer support mechanism of  claim 1 , wherein said second layer is fabricated of a polymer. 
   
   
       7 . The wafer support mechanism of  claim 1 , wherein said second layer is fabricated of a ceramic. 
   
   
       8 . The wafer support mechanism of  claim 1 , wherein said plurality of electrodes comprises six electrode segments. 
   
   
       9 . The wafer support mechanism of  claim 1 , wherein each of said plurality of electrodes is selectively energized. 
   
   
       10 . The wafer support mechanism of  claim 1 , wherein said channel is configured to have a counter-flow pattern having a fluid flow in at least two opposite directions.