Methods and systems for controlling accumulation of electrical charge during semiconductor etching processes

Abstract

A method and system are provided for controlling the accumulation of electrical charge during a semiconductor plasma etching process performed in a plasma etching chamber. The bias voltage supplied to the plasma etching chamber is modulated by a bias power modulation circuit to control the accumulation of electrical charge and to force the accumulated electrical charge to be periodically discharged at a controlled rate of discharge that prevents the wafer from being damaged.

1 . A system for controlling an accumulation of electrical charge on a wafer located in a plasma etching chamber during a plasma etching process, the system comprising:
 bias supply voltage control circuitry configured to provide a supply voltage that alternates at a selected frequency between a first supply voltage level and a second supply voltage level; and   bias power modulation circuitry configured to receive the alternating first and second supply voltage levels and to bias the plasma etching chamber at first and second bias voltage levels in response to receiving the first and second supply voltage levels, respectively.   
   
   
       2 . The bias supply voltage control circuitry comprising:
 a control logic unit (CLU) electrically coupled to a bias power supply, the CLU being configured to generate a control signal that is provided to the bias power supply, the control signal having at least a first state and a second state, the control signal causing the bias power supply to output the first supply voltage level if the control signal is in the first state and to output the second supply voltage level if the control signal is in the second state.   
   
   
       3 . The system of  claim 2 , wherein the CLU is configured to alternate the control signal between the first and second states at a selected frequency such that the control signal is maintained at the first state for a first time period and at the second state for a second time period, and wherein when the control signal is maintained at the first state for the first time period, the bias power modulation circuit provides the first bias voltage level to the chamber for a third time period, and wherein when the control signal is maintained at the second state for the second time period, the bias power modulation circuit provides the second bias voltage level to the chamber for a fourth time period. 
   
   
       4 . The system of  claim 3 , wherein the third time period corresponds to a discharge cycle during which accumulated electrical charge on one or more surfaces of the wafer is discharged from the chamber, and wherein the fourth time period corresponds to an etching cycle during which one or more surfaces of the wafer are etched by a plasma in the chamber, the third time period being shorter than the second time period. 
   
   
       5 . The system of  claim 3 , wherein the CLU is programmable, and wherein the selected frequency at which the control signal alternates between the first and second states is set by programming the CLU with instructions that cause the control signal to alternate between the first and second states at the selected frequency. 
   
   
       6 . The system of  claim 5 , wherein the selected frequency is part of an etch recipe that is loaded into the CLU from a computer that controls the plasma etching process. 
   
   
       7 . The system of  claim 6 , wherein the fourth time period corresponding to the etching cycle is variable for different etching steps of a same recipe and wherein the third time period corresponding to the discharge cycle generally remains constant over different etch recipes. 
   
   
       8 . The system of  claim 1 , wherein when the bias power modulation circuit provides the first bias voltage level to the chamber, accumulated electrical charges on one or more surfaces of the wafer are discharged from the chamber at a controlled discharge rate, the controlled discharge rate being determined by the configuration of the bias power modulation circuitry. 
   
   
       9 . The system of  claim 8 , wherein the bias power modulation circuit is configured with a discharge network comprising one or more resistors and one or more inductors that together limit the discharge of accumulated charge to provide the controlled discharge rate. 
   
   
       10 . A system for controlling an accumulation of electrical charge on a wafer located in a plasma etching chamber during a plasma etching process, the system comprising:
 a control logic unit (CLU), the CLU being electrically coupled to a bias power supply and being configured to generate a control signal that is provided to the bias power supply, the control signal having at least a first state and a second state, the control signal causing the bias power supply to output a first supply voltage level if the control signal is in the first state and to output a second supply voltage level if the control signal is in the second state; and   a bias power modulation circuit, the bias power modulation circuit being electrically coupled to the bias power supply and to a bias voltage terminal of the etching chamber, the bias power modulation circuit receiving the first supply voltage level output from the bias power supply when the control signal is in the first state and receiving the second supply voltage level output from the bias power supply when the control signal is in the second state, wherein when the bias power modulation circuit receives the first supply voltage level, the bias power modulation circuit provides a first bias voltage level to the chamber via the bias voltage terminal, and wherein when the bias power modulation circuit receives the second supply voltage level, the bias power modulation circuit provides a second bias voltage level to the chamber, wherein when the bias power modulation circuit provides the first bias voltage level to the chamber, accumulated electrical charges on one or more surfaces of the wafer are discharged from the chamber.   
   
   
       11 . The system of  claim 10 , wherein the CLU is configured to alternate the control signal between the first and second states at a selected frequency such that the control signal is maintained at the first state for a first time period and at the second state for a second time period, and wherein when the control signal is maintained at the first state for the first time period, the bias power modulation circuit provides the first bias voltage level to the chamber for a third time period, and wherein when the control signal is maintained at the second state for the second time period, the bias power modulation circuit provides the second bias voltage level to the chamber for a fourth time period. 
   
   
       12 . The system of  claim 11 , wherein the third time period corresponds to a discharge cycle during which accumulated electrical charge on one or more surfaces of the wafer is discharged from the chamber, and wherein the fourth time period corresponds to an etching cycle during which one or more surfaces of the wafer are etched by a plasma in the chamber, the third time period being shorter than the second time period. 
   
   
       13 . The system of  claim 11 , wherein the CLU is programmable, and wherein the selected frequency at which the control signal alternates between the first and second states is set by programming the CLU with instructions that cause the control signal to alternate between the first and second states at the selected frequency. 
   
   
       14 . A method for controlling an accumulation of electrical charge on a wafer located in a plasma etching chamber during a plasma etching process, the method comprising:
 placing a wafer in a plasma etching chamber;   applying a radio frequency (RF) electrical field and a bias electrical field to the chamber;   modulating the bias electrical field between a first bias voltage level and a second bias voltage level; and   after the etching process has been completed, removing the wafer from the chamber.   
   
   
       15 . The method of  claim 14 , wherein modulating the bias electrical field between a first bias voltage level and a second bias voltage level comprises:
 with bias supply voltage control circuitry, supplying a supply voltage that alternates at a selected frequency between a first supply voltage level and a second supply voltage level; and   with bias power modulation circuitry, receiving the alternating first and second supply voltage levels and biasing the plasma etching chamber at the first and second bias voltage levels in response to receiving the first and second supply voltage levels, respectively.   
   
   
       16 . The method of  claim 15 , further comprising:
 with a control logic unit (CLU) of the supply voltage control circuitry, generating a control signal; and   in a bias power supply of the supply voltage control circuitry, receiving the control signal, the control signal having at least a first state and a second state, the control signal causing the bias power supply to output the first supply voltage level if the control signal is in the first state and to output the second supply voltage level if the control signal is in the second state.   
   
   
       17 . The method  claim 16 , further comprising:
 with the CLU, alternating the control signal between the first and second states at a selected frequency such that the control signal is maintained at the first state for a first time period and at the second state for a second time period;   with the bias power modulation circuit, providing the first bias voltage level to the chamber for a third time period when the control signal is maintained at the first state for the first time period; and   with the bias power modulation circuit, providing the second bias voltage level to the chamber for a fourth time period when the control signal is maintained at the second state for the second time period.   
   
   
       18 . The method of  claim 17 , wherein the third time period corresponds to a discharge cycle during which accumulated electrical charge on one or more surfaces of the wafer is discharged from the chamber, and wherein the fourth time period corresponds to an etching cycle during which one or more surfaces of the wafer are etched by a plasma in the chamber, the third time period being shorter than the second time period. 
   
   
       19 . The method of  claim 17 , wherein the CLU is programmable, and wherein the selected frequency at which the control signal alternates between the first and second states is set by programming the CLU with instructions that cause the control signal to alternate between the first and second states at the selected frequency. 
   
   
       20 . The method of  claim 19 , wherein the selected frequency is part of an etch recipe that is loaded into the CLU from a computer that controls the plasma etching process. 
   
   
       21 . A system for controlling an accumulation of electrical charge on a wafer located in a plasma etching chamber during a plasma etching process, the system comprising:
 a chamber into which a wafer to be etched is loaded, the chamber having first and second bias voltage terminals that are at first and second bias potentials, respectively; and   etching process control circuitry configured to cause electrical charge that accumulates on the wafer during a plasma etching process to be discharged at least one time during the plasma etching process.   
   
   
       22 . The system of  claim 21 , wherein the etching process control circuitry is configured to cause electrical charge that accumulates on the wafer during a plasma etching process to be discharged multiple times during the plasma etching process. 
   
   
       23 . The system of  claim 22 , wherein the etching process control circuitry is configured to cause electrical charge that accumulates on the wafer during a plasma etching process to be discharged multiple times during the plasma etching process, and to be discharged at least one time before the etching process begins and at least one time after the etching process has ended.