US2009139244A1PendingUtilityA1

Devices for cooling and power

43
Assignee: SCHLUMBERGER TECHNOLOGY CORPPriority: Nov 30, 2007Filed: Nov 30, 2007Published: Jun 4, 2009
Est. expiryNov 30, 2027(~1.3 yrs left)· nominal 20-yr term from priority
Inventors:John UlloTsutomu YamateJiro Takeda
H10W 40/28F25B 21/02Y10T29/4935H10N 10/857
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Claims

Abstract

Certain embodiments disclosed herein are directed to devices for cooling. In certain examples, a thermoelectric device comprising a substrate and a superlattice coupled to the substrate is disclosed. In some examples, the superlattice includes a first semi-conducting material and a second semi-conducting material coupled to the first semi-conducting material to provide an interface between the first and second semi-conducting materials.

Claims

exact text as granted — not AI-modified
1 ) A hybrid thermoelectric cooler (TEC), said TEC comprising:
 at least one first TEC stage, said first stage having a first set of TEC properties;   at least one second TEC stage, said second stage having a second set of TEC properties, said at least one second TEC stage in communication with said at least one first TEC stage to form a hybrid TEC cooler;   wherein the properties of the hybrid TEC cooler include properties from the at least one first TEC stage and second TEC stage.   
   
   
       2 ) The hybrid TEC of  claim 1 , wherein the properties of the Hybrid TEC included complementary properties from the at least one first TEC stage and second TEC stage. 
   
   
       3 ) The at least one first TEC stage of  claim 1 , wherein said at least one first TEC stage is at least one bulk TEC stage. 
   
   
       4 ) The at least one bulk TEC stage of  claim 3 , wherein said first set of properties is a large temperature differential property. 
   
   
       5 ) The at least one second TEC stage of  claim 1 , wherein said at least one second TEC stage is at least one nano TEC stage. 
   
   
       6 ) The nano TEC stage of  claim 5 , wherein said nano TEC stage is a superlattice structure. 
   
   
       7 ) The nano TEC stage of  claim 5 , wherein said nano TEC stage is an amorphous structure. 
   
   
       8 ) The at least one nano TEC stage of  claim 5 , wherein said second set of properties is an efficient heat transfer property. 
   
   
       9 ) The bulk TEC stage of  claim 3 , wherein said bulk TEC stage provides a greater temperature difference than the nano TEC stage. 
   
   
       10 ) The nano TEC stage of  claim 5 , wherein said nano TEC stage provides more efficient heat transfer than the bulk TEC stage. 
   
   
       11 ) The hybrid TEC of  claim 1 , wherein said complementary properties of the hybrid TEC are increased heat transfer efficiency and large temperature differential properties. 
   
   
       12 ) The hybrid TEC of  claim 1 , wherein the first TEC stage and second TEC stage of said hybrid are of approximately similar size. 
   
   
       13 ) The hybrid TEC of  claim 1 , further comprising multiple first and second TEC stages in communication with each other. 
   
   
       14 ) The hybrid TEC of  claim 1 , wherein said communication is thermal communication. 
   
   
       15 ) The hybrid TEC of  claim 1 , wherein said hybrid TEC is deployed in a downhole environment. 
   
   
       16 ) The hybrid TEC of  claim 1 , wherein said hybrid TEC is in thermal communication with an electrical component. 
   
   
       17 ) The hybrid TEC of  claim 1 , wherein said hybrid TEC is in thermal communication with at least one heat sink through at least one thermal interface. 
   
   
       18 ) The hybrid TEC of  claim 1 , wherein said hybrid TEC further comprises at least one insulator, said insulator providing an insulative interface between the hybrid TEC and an environment external to the hybrid TEC. 
   
   
       19 ) The insulator of  claim 18 , wherein said insulator is one of the group comprising an insulative material, an air gap, an inert gas or a vacuum. 
   
   
       20 ) The hybrid TEC of  claim 1 , further comprising at least one heat reflection treatment associated with the hybrid TEC. 
   
   
       21 ) They hybrid TEC of  claim 1 , further comprising at least one surface treatment associated with the hybrid TEC. 
   
   
       22 ) The hybrid TEC of  claim 1 , wherein said hybrid TEC cools an associated electronic component to below ambient temperature. 
   
   
       23 ) The hybrid TEC of  claim 1 , wherein said hybrid TEC cools an associated electronic component to approximately ambient temperature. 
   
   
       24 ) A method for fabricating a hybrid TEC cooler, comprising the steps of:
 providing at least one first TEC stage, said first stage having a first set of TEC properties;   providing at least one second TEC stage, said second stage having a second set of TEC properties;   establishing thermal communication between said at least one first and second TEC stage to form a hybrid TEC cooler, wherein the properties of the hybrid TEC cooler include properties from the at least one first TEC stage and second TEC stage.   
   
   
       25 ) The method of  claim 24 , wherein the properties of the Hybrid TEC included complementary properties from the at least one first TEC stage and second TEC stage. 
   
   
       26 ) The at least one first TEC stage of  claim 24 , wherein said at least one first TEC stage is at least one bulk TEC stage. 
   
   
       27 ) The at least one bulk TEC stage of  claim 25 , wherein said first set of properties is a large temperature differential property. 
   
   
       28 ) The at least one second TEC stage of  claim 24 , wherein said at least one second TEC stage is at least one nano TEC stage. 
   
   
       29 ) The nano TEC stage of  claim 28 , wherein said nano TEC stage is a superlattice structure. 
   
   
       30 ) The nano TEC stage of  claim 28 , wherein said nano TEC stage is an amorphous structure. 
   
   
       31 ) The at least one nano TEC stage of  claim 24 , wherein said second set of properties is an efficient heat transfer property. 
   
   
       32 ) The method of  claim 24 , further comprising the step of providing a first and second TEC stage of substantially similar size. 
   
   
       33 ) The method of  claim 24 , further comprising the step of establishing thermal communication between the hybrid TEC and an electrical component. 
   
   
       34 ) The method of  claim 24 , further comprising the step of thermally communicating with at least one heat sink through at least one thermal interface. 
   
   
       35 ) The method of  claim 24 , further comprising the step of providing at least one insulator, said insulator providing an insulative interface between the hybrid TEC and an environment external to the hybrid TEC. 
   
   
       36 ) The method of  claim 24 , further comprising associating at least one heat reflection treatment with the hybrid TEC. 
   
   
       37 ) They method of  claim 24 , further comprising associating at least one surface treatment associated with the hybrid TEC. 
   
   
       38 ) A multistage hybrid TEC, said multistage hybrid TEC comprising:
 one or more bulk TECs capable of providing large temperature differential properties;   one or more nano TECs capable of providing efficient heat transfer properties;   wherein said bulk TECs and nano TECs are in thermal contact with each other to provide a multistage hybrid TEC having a large temperature differential and efficient heat transfer properties.   
   
   
       39 ) The multistage hybrid TEC of  claim 38 , wherein said multistage hybrid TEC is suitable for use downhole. 
   
   
       40 ) The multistage hybrid TEC of  claim 38 , wherein said multistage hybrid TEC is suitable for use in cooling an integrated circuit. 
   
   
       41 ) The multistage hybrid TEC of  claim 38 , wherein said multistage hybrid TEC is suitable for use in cooling a printed circuit board.

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