Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit

Abstract

A cell according to the present invention comprises a plurality of terminals capable of transmitting an input signal or an output signal and serving as a minimum unit in designing a semiconductor integrated circuit, wherein the plurality of terminals is located on routing grids lined in a Y direction which is a direction vertical to a power-supply wiring of the cell used in automatic placement & routing and has a shape extended in an X direction which is a direction in parallel with the power-supply wiring, more specifically such a shape that, for example, a longer-side dimension of the terminal is equal to “a routing grid interval in the X direction+a wiring width. According to the constitution, a cell area is reduced, which advantageously leads to the reduction of a chip area.

1 - 33 . (canceled) 
   
   
       34 . A standard cell comprising a plurality of gate electrodes, wherein
 a cell width of the standard cell along an X direction in parallel with a power-supply wiring of the standard cell is an integral multiple of a numeral value different to a routing grid interval along the X direction.   
   
   
       35 . A standard cell comprising a plurality of gate electrodes, wherein
 said plurality of gate electrodes are arranged in an X direction in parallel with a power-supply wiring for supplying electric potentials to the standard cell,   each of said plurality of gate electrodes extends in a Y direction which is orthogonally-crossed with the X direction, and   a gate pitch of said plurality of gate electrodes is different to a routing grid interval along the X direction.   
   
   
       36 . A standard cell according to  claim 35 , wherein
 a wiring is placed on an upper side of the standard cell, and   said wiring is placed on said routing grid.   
   
   
       37 . A standard cell according to  claim 35 , wherein
 a wiring is placed on an upper side of the standard cell,   said plurality of gate electrodes are connected to said wiring through a terminal,   a shorter-side dimension of said terminal corresponds to a wiring width in an automatic placement & routing, and   a longer-side dimension of said terminal is at least longer than the length of said routing grid interval along said X direction and at most shorter than the length obtained by subtracting a minimum wiring interval from a cell width of the standard cell along said X direction.   
   
   
       38 . A standard cell according to  claim 35 , wherein
 a wiring is placed on an upper side of the standard cell,   said plurality of gate electrodes are connected to said wiring through a terminal,   a shorter-side dimension of said terminal corresponds to a wiring width in an automatic placement & routing, and   a longer-side dimension of said terminal is at least longer than the length of “said routing grid interval along said X direction+said wiring width” and at most shorter than the length obtained by subtracting a minimum wiring interval from a cell width of the standard cell along said X direction.   
   
   
       39 . A standard cell according to  claim 35 , wherein
 a wiring is placed on an upper side of the standard cell, and   said plurality of gate electrodes are connected to said wiring through a terminal,   a shorter-side dimension of said terminal corresponds to a wiring width in an automatic placement & routing, and   a longer-side dimension of said terminal corresponds to the length of “said routing grid interval along said X direction+said wiring width”.   
   
   
       40 . A standard cell according to  claim 35 , wherein
 a wiring is placed on an upper side of the standard cell,   said plurality of gate electrodes are connected to said wiring through a terminal,   a shorter-side dimension of said terminal corresponds to a wiring width in an automatic placement & routing, and   a longer-side dimension of said terminal corresponds to the length obtained by subtracting a minimum wiring interval from a cell width of the standard cell along said X direction.   
   
   
       41 . A semiconductor integrated circuit, wherein
 a plurality of the standard cell according to  claim 35  is placed in parallel along said X direction.   
   
   
       42 . A semiconductor integrated circuit according to  claim 41 , wherein
 a dummy gate is provided between adjacent standard cells.   
   
   
       43 . A semiconductor integrated circuit according to  claim 42 , wherein
 a central line extending along the Y direction of said dummy gate is located at a point midway between said adjacent standard cells.   
   
   
       44 . A semiconductor integrated circuit according to  claim 41 , wherein
 said plurality of standard cells includes a first standard cell located on an end of a cell row and a second standard cell being adjacent with said first standard cell,   a cell boundary between said first standard cell and said second standard cell is provided at a point midway between an end portion of a second standard cell side of a diffusion region of said first standard cell and an end portion of a first standard cell side of a diffusion region of said second standard cell.