Multiplier device with suppression of higher-order distortion

Abstract

A multiplier device is configured to include first to n th multipliers M 1 to M n for multiplying a carrier modulated information signal with first to n th mutually phase shifted and identical, substantially square wave mixing signals MS 1 to MS n with 50% duty cycle. In order to eliminate fifth or higher order interferences from the output of the multiplier device according to the invention, n is greater than 2, outputs of the multipliers M 1 to M n are respectively coupled through weighting circuits W 1 to W n with respective fixed weighting factors WF 1 to WF n to an adder circuit, the mixing signals MS 1 to MS n having respective phase angles φ i corresponding to φ i =i*Δφ, the weighting factors WF i corresponding to the sine value of the respective phase angles φ i =i*Δφ with Δφ being the mutual phase difference between each two phase consecutive mixing signals corresponding to π/(n+1) and i varying from 1 to n.

1 . A method for execution in a signal processing system comprising:
 receiving an input signal;   generating a number of mixing signals, the number of mixing signals being greater than two, each mixing signal having a common frequency and different phase;   multiplying the input signal by each of the mixing signals to produce a plurality of intermediate signals, and   combining all of the intermediate signals to provide an output signal.   
   
   
       2 . The method of  claim 1 , wherein the combining includes providing a weighted sum of the intermediate signals. 
   
   
       3 . The method of  claim 2 , wherein each intermediate signal has a weight for determining the weighted sum that corresponds to a sine of the phase of the corresponding mixing signal. 
   
   
       4 . The method of  claim 3 , wherein each mixing signal has a 50% duty cycle. 
   
   
       5 . The method of  claim 4 , wherein each mixing signal differs in phase from another mixing signal by π/(n+1), where n equals the number of mixing signals. 
   
   
       6 . The method of  claim 3 , wherein each mixing signal differs in phase from another mixing signal by π/(n+1), where n equals the number of mixing signals. 
   
   
       7 . The method of  claim 2 , wherein each mixing signal differs in phase from another mixing signal by π/(n+1), where n equals the number of mixing signals. 
   
   
       8 . The method of  claim 1 , wherein each mixing signal differs in phase from another mixing signal by π/(n+1), where n equals the number of mixing signals. 
   
   
       9 . The method of  claim 1 , wherein generating the mixing signals includes generating a local oscillator signal, delaying the local oscillator signal via a string of delay devices, wherein each mixing signal corresponds to an output of each delay device. 
   
   
       10 . The method of  claim 9 , wherein each delay device delays the local oscillator signal by P/2(n+1), where P corresponds to a period of the local oscillator signal, and n equals the number of mixing signals. 
   
   
       11 . The method of  claim 9 , wherein generating the mixing signal includes dividing the local oscillator signal by a factor of n to provide a clocking signal, where n equals the number of mixing signals, and clocking each of the delay devices with the clocking signal to provide each of the mixing signals. 
   
   
       12 . A computer program stored on a computer-readable medium that, when executed by a signal processor, causes the processor to:
 receive an input signal;   generate a number of mixing signals, the number of mixing signals being greater than two, each mixing signal having a common frequency and different phase;   multiply the input signal by each of the mixing signals to produce a plurality of intermediate signals, and   combine all of the intermediate signals to provide an output signal.   
   
   
       13 . The program of  claim 12 , wherein the program is configured to cause the processor to combine the intermediate signals by accumulating a weighted sum of the intermediate signals. 
   
   
       14 . The program of  claim 13 , wherein each intermediate signal has an associated weight for accumulating the weighted sum that corresponds to a sine of the phase of the corresponding mixing signal. 
   
   
       15 . The program of  claim 14 , wherein each mixing signal has a 50% duty cycle. 
   
   
       16 . The program of  claim 15 , wherein each mixing signal differs in phase from another mixing signal by π/(n+1), where n equals the number of mixing signals. 
   
   
       17 . The program of  claim 14 , wherein each mixing signal differs in phase from another mixing signal by π/(n+1), where n equals the number of mixing signals. 
   
   
       18 . The program of  claim 13 , wherein each mixing signal differs in phase from another mixing signal by π/(n+1), where n equals the number of mixing signals. 
   
   
       19 . The program of  claim 12 , wherein each mixing signal differs in phase from another mixing signal by π/(n+1), where n equals the number of mixing signals. 
   
   
       20 . The program of  claim 12 , wherein the processor is configured to receive a local oscillator signal, and the program is configured to cause the processor to generate each mixing signal via a series of delays, each delay being substantially equal to P/2(n+1), where P corresponds to a period of the local oscillator signal, and n equals the number of mixing signals.