Synchronization of parallel processes

Abstract

A speculative execution capability of a processor is exposed to program control through at least one machine instruction. The at least one machine instruction may be two instructions designed to facilitate synchronization between parallel processes. According to an aspect, an instruction set architecture includes circuitry that handles a speculative execution instruction and a speculation termination instruction. The speculative execution instruction may be an instruction that takes first and second operands, causes the processor to speculatively execute additional instructions if a memory location contains a value, and causes the processor to start executing instructions from an address indicated by the second operand if a mis-speculation occurs, and the speculation termination instruction may be an instruction that causes the processor to begin retiring the additional instructions.

1 . A processor comprising:
 a front end that obtains instructions; and   a back end that provides speculative execution of the instructions;   wherein the processor includes an instruction set architecture and speculative execution control circuitry that handles at least one machine instruction that facilitates synchronization between parallel processes by exposing processor speculation of synchronization lock acquisition code to program control;   wherein the processor speculation checks for a dependency violation during acquisition of the synchronization lock.   
   
   
       2 . The processor of  claim 1 , wherein
 the at least one machine instruction of the instruction set architecture comprises a speculative execution instruction and a speculation termination instruction,   the speculative execution instruction causes the processor to speculatively execute additional instructions, and   the speculation termination instruction causes the processor to begin retiring the additional instructions.   
   
   
       3 . The processor of  claim 2 , wherein the front end comprises an in-order front end, and the back end comprises an out-of-order execution engine, which re-orders the instructions, and an execution unit that perform the re-ordered instructions. 
   
   
       4 . The processor of  claim 3 , wherein the out-of-order execution engine comprises an out-of-order execution management unit, including at least one buffer, and an in-order retire-store unit. 
   
   
       5 . The processor of  claim 4 , wherein the at least one buffer comprises a reorder buffer. 
   
   
       6 . The processor of  claim 2 , wherein the front end comprises a fetch-decode unit and a branch prediction unit. 
   
   
       7 . The processor of  claim 2 , wherein the processor speculation checks for an interrupt during acquisition of the synchronization lock. 
   
   
       8 . The processor of  claim 2 , wherein the speculative execution instruction takes two operands, and the speculation termination instruction takes two operands. 
   
   
       9 . A machine-implemented method comprising:
 generating parallel processes in a data processing machine;   effecting synchronization between the parallel processes using processor speculation in the data processing machine to speculatively execute one or more instructions that read-modify-write a lock variable associated with a critical section; and   providing output resulting from the synchronized parallel processes.   
   
   
       10 . The method of  claim 9 , wherein said effecting synchronization comprises ending speculative execution of the one or more instructions that read-modify-write the lock variable before performing the critical section. 
   
   
       11 . The method of  claim 10 , wherein said effecting synchronization comprises placing in an out-of-order execution management unit of a processor, at least one machine instruction that limits when other machine instructions are retired from the out-of-order execution management unit. 
   
   
       12 . The method of  claim 11 , wherein said effecting synchronization comprises translating at least one high-level software instruction into at least one machine instruction that controls speculative execution in a processor. 
   
   
       13 . The method of  claim 12 , wherein said generating parallel processes comprises running a software program that spawns multiple threads in the data processing machine. 
   
   
       14 . The method of  claim 12 , wherein said providing output comprises sending the output to another data processing machine. 
   
   
       15 . An article comprising a machine-readable storage medium embodying information indicative of instructions that when performed by one or more machines result in operations comprising:
 generating parallel processes in a data processing machine;   effecting synchronization between the parallel processes using processor speculation in the data processing machine to speculatively execute one or more instructions that read-modify-write a lock variable associated with a critical section; and   providing output resulting from the synchronized parallel processes.   
   
   
       16 . The article of  claim 15 , wherein said effecting synchronization comprises ending speculative execution of the one or more instructions that read-modify-write the lock variable before performing the critical section. 
   
   
       17 . The article of  claim 16 , wherein said effecting synchronization comprises placing in an out-of-order execution management unit of a processor, at least one machine instruction that limits when other machine instructions are retired from the out-of-order execution management unit. 
   
   
       18 . The article of  claim 17 , wherein said effecting synchronization comprises translating at least one high-level software instruction into at least one machine instruction that controls speculative execution in a processor. 
   
   
       19 . The article of  claim 18 , wherein said generating parallel processes comprises running a software program that spawns multiple threads in the data processing machine. 
   
   
       20 . The article of  claim 18 , wherein said providing output comprises sending the output to another data processing machine.