Non-Volatile Memory Device with Improved Immunity to Erase Saturation and Method for Manufacturing Same

Abstract

A non-volatile memory device having a control gate on top of the second dielectric (interpoly or blocking dielectric), at least a bottom layer of the control gate in contact with the second dielectric being constructed in a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k materials after full device fabrication. At least a top layer of the second dielectric, separating the bottom layer of the control gate from the rest of the second dielectric, is constructed in a predetermined high-k material, chosen outside the group for avoiding a reduction in the work-function of the material of the bottom layer of the control gate. In the manufacturing method, the top layer is created in the second dielectric before applying the control gate.

1 . A non-volatile memory device, comprising:
 a substrate comprising a channel between two doped regions;   a first dielectric on top of the channel, the first dielectric being a tunnel dielectric;   a charge storage medium on top of the tunnel dielectric;   a second dielectric on top of the charge storage medium;   a control gate on top of the second dielectric, at least a bottom layer of the control gate in contact with the second dielectric comprising a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k materials after full device fabrication; and   
       wherein at least a top layer of the second dielectric, separating the bottom layer of the control gate from the rest of the second dielectric, comprises a predetermined high-k material, chosen outside the group for avoiding a reduction in the work-function of the material of the bottom layer of the control gate. 
     
     
         2 . The non-volatile memory device according to  claim 1 , wherein at least an upper part of the second dielectric comprises a high-k material of the group, the top layer being formed by a nitrided part of the high-k material. 
     
     
         3 . The non-volatile memory device according to  claim 2 , wherein the second dielectric is substantially completely constructed in the nitrided high-k material. 
     
     
         4 . The non-volatile memory device according to  claim 1 , wherein the top layer is formed by a capping layer on top of a high-k layer of the second dielectric which comprises a high-k material of the group. 
     
     
         5 . The non-volatile memory device according to  claim 4 , wherein the capping layer comprises AlN or AlON. 
     
     
         6 . The non-volatile memory device according to  claim 1 , wherein the group of high-k materials comprises Al2O3, HfSiO, HfAlO and HfLaO. 
     
     
         7 . The non-volatile memory device according to  claim 1 , wherein the material of at least the bottom layer of the control gate is chosen such that its work-function is above the work-function of the material of the channel. 
     
     
         8 . The non-volatile memory device according to  claim 7 , wherein the material of at least the bottom layer of the control gate comprises a material with metallic characteristics, such as for example a metal or a metallic compound. 
     
     
         9 . The non-volatile memory device according to  claim 8 , wherein the control gate comprises a thin screening layer as the bottom layer with a thick polysilicon layer on top, forming a metal inserted polysilicon structure. 
     
     
         10 . The non-volatile memory device according to  claim 7 , wherein the control gate is substantially completely constructed in a p-type semiconductor material. 
     
     
         11 . The non-volatile memory device according to  claim 1 , wherein the charge storage medium is formed by a conductive floating gate. 
     
     
         12 . The non-volatile memory device according to  claim 1 , wherein the charge storage medium is formed by a charge trapping layer. 
     
     
         13 . A method for manufacturing a non-volatile memory device, comprising the steps of:
 providing a substrate comprising a channel between two doped regions;   applying a first dielectric on top of the channel, the first dielectric being a tunnel dielectric;   applying a charge storage medium on top of the tunnel dielectric;   applying a second dielectric on top of the charge storage medium; and   applying a control gate on top of the second dielectric, at least a bottom layer of the control gate in contact with the second dielectric comprises a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k materials after full device fabrication;   wherein before applying the control gate, at least a top layer is constructed in the second dielectric for separating the control gate from the rest of the second dielectric, the top layer comprising a predetermined material, chosen outside the group for avoiding a reduction in the work-function of the material of the control gate.   
     
     
         14 . The method according to  claim 13 , wherein at least an upper part of the second dielectric comprises a high-k material of the group, the top layer being constructed by nitridation of the high-k material. 
     
     
         15 . The method according to  claim 14 , wherein the second dielectric is substantially completely constructed in the high-k material which is substantially completely nitrided. 
     
     
         16 . The method according to  claim 13 , wherein the nitridation comprises a decoupled plasma nitridation. 
     
     
         17 . The method according to  claim 13 , wherein the nitridation comprises an ammonia anneal step. 
     
     
         18 . The method according to  claim 13 , wherein the second dielectric comprises a high-k layer which comprises a high-k material of the group, the top layer being constructed by applying a capping layer on top of the high-k layer. 
     
     
         19 . The method according to  claim 18 , wherein the capping layer comprises AlN or AlON. 
     
     
         20 . The method according to  claim 13 , wherein the group of high-k materials comprises Al2O3, HfSiO, HfAlO and HfLaO. 
     
     
         21 . The method according to  claim 13 , wherein the material of at least the bottom layer of the control gate is chosen such that its work-function is above the work-function of the material of the channel. 
     
     
         22 . The method according to  claim 21 , wherein the material of at least the bottom layer of the control gate is a material with metallic characteristics, such as for example a metal or a metallic compound. 
     
     
         23 . The method according to  claim 22 , wherein the control gate comprises a thin screening layer as the bottom layer and a thick polysilicon layer on top, forming a metal inserted polysilicon structure. 
     
     
         24 . The method according to  claim 21 , wherein the control gate is substantially completely constructed in a p-type semiconductor material.