Integrated electronic circuit incorporating a capacitor

Abstract

A non-volatile memory element includes a transistor for selecting the element and a capacitor for recording a binary value by electrical breakdown of an insulating layer of the capacitor. A structure of the memory element is modified in order to allow a higher degree of integration of the element within an electronic circuit of the MOS type. In addition, the memory element is made more robust with respect to a high electrical voltage (VDD) used for recording the binary value. The transistor includes a drain in the substrate with electric field drift in a longitudinal direction extending towards the capacitor. The electric field drift region for the drain includes a first extension underneath the gate of the transistor opposite the source and a second extension underneath the insulating layer of the capacitor. Doping of the substrate for the electric field drift region is limited to a region substantially corresponding to a distance between the gate and an electrode of the capacitor.

1 . An integrated electronic circuit comprising:
 a non-volatile memory element comprising a MOS transistor having a source in a substrate, a gate and a drain in the substrate with electric field drift in a longitudinal direction, and further comprising a capacitor having a first electrode is arranged on an insulating layer and a second electrode comprising a first portion of the substrate located under the insulating layer and aligned with the drain in the longitudinal direction, wherein the electric field drift of the drain is formed in a second portion of the substrate adjacent the first portion and extending along the longitudinal direction from a first extension underneath the gate of the transistor opposite the source to a second extension underneath the insulating layer of the capacitor.   
   
   
       2 . The circuit according to  claim 1 , wherein the circuit is a random access memory array formed from a plurality of said non-volatile memory elements. 
   
   
       3 . The circuit according to  claim 1 , wherein a doping of said second portion is limited to a region substantially corresponding to a distance between the gate and the first electrode along the longitudinal direction. 
   
   
       4 . The circuit according to  claim 1 , wherein the second portion of the substrate corresponding to the electric field drift of the drain has a concentration of n-type dopant species of around 5×10 18  cm −3 . 
   
   
       5 . The circuit according to  claim 4 , wherein the first portion of the substrate corresponding to the second electrode of the capacitor has a concentration of n-type dopant species of around 5×10 17  cm −3 . 
   
   
       6 . The circuit according to  claim 1 , wherein the transistor comprises a gate isolation layer having a thickness greater than or equal to a thickness of the insulating layer of the capacitor. 
   
   
       7 . The circuit according to  claim 1 , wherein the second portion of the substrate corresponding to the electric field drift of the drain has an identical doping to a doping of the first extension under the gate of the transistor. 
   
   
       8 . The circuit according to  claim 1 , wherein the second portion of the substrate corresponding to the electric field drift of the drain has an identical doping to a doping of the second extension under the insulating layer of the capacitor. 
   
   
       9 . The circuit according to  claim 1 , wherein the transistor and capacitor are formed in an active region of the substrate defined within an encircling isolation ring, the active region having a substrate surface area of less than 7 μm 2 . 
   
   
       10 . The circuit according to  claim 11 , wherein the transistor and capacitor are formed in an active region of the substrate defined within an encircling isolation ring, the active region having a substrate surface area of less than 5 μm 2 . 
   
   
       11 . The circuit according to  claim 1 , wherein the transistor and capacitor are formed in an active region of the substrate defined within an encircling isolation ring, the active region having a substrate surface area of about 3 μm 2 . 
   
   
       12 . The circuit according to  claim 1 , wherein second portion of the substrate forms a resistance protecting the transistor from damage during breakdown of the insulating layer of the capacitor to store a data value. 
   
   
       13 . A process for the fabrication of a non-volatile memory element, within an integrated electronic circuit, for the storage of one bit, said memory element comprising a capacitor for recording a value of the bit by breakdown of an insulating layer of said capacitor and a transistor for selecting said element, the transistor and the capacitor being formed within an active region of an integrated electronic circuit substrate,
 wherein the transistor is of the field-effect MOS type and incorporates a source region designed to be connected to a first power supply terminal for the memory element, a gate designed to be connected to a selection terminal for the memory element, and a drain region with electric field drift in a longitudinal direction,   wherein the capacitor incorporates the insulating layer arranged on top of a surface of the substrate, a first electrode of the capacitor is arranged on the insulating layer and designed to be connected to a second power supply terminal for the memory element, and a second electrode of the capacitor comprising a first portion of the substrate located under the insulating layer and in line with the drain region of the transistor on a side opposite to the gate,   the process comprising:   providing the drift-field drain region within the active region with a second portion of the substrate that is determined by self-alignment with respect to the gate and the first electrode parallel to the longitudinal direction,   wherein providing is accomplished during doping of said second portion of the substrate.   
   
   
       14 . The process according to  claim 13 , further comprising doping the second portion of the substrate corresponding to the drift-field drain region at the same time as extensions of source and of drain regions of MOS transistors contained in the circuit. 
   
   
       15 . The process according to  claim 13 , further comprising forming the first electrode and the insulating layer of the capacitor at the same time as gates and gate isolation layers of MOS transistors contained in the circuit. 
   
   
       16 . The process according to  claim 13 , further comprising doping a part of the first portion of the substrate corresponding to the second electrode of the capacitor at the same time as portions of the substrate designed to form the channels of MOS transistors contained in the circuit for adjusting a threshold voltage of said transistors. 
   
   
       17 . The process according to  claim 13 , further comprising forming a gate isolation layer of the transistor with a thickness e 2  that is greater than or equal to a thickness e 1  of the insulating layer of the capacitor, said thicknesses being measured in a direction perpendicular to the surface of the substrate. 
   
   
       18 . The process according to  claim 13 , further comprising doping the second portion of the substrate corresponding to the drift-field drain region at the same time as extensions of source and of drain regions of MOS transistors contained in the circuit, and forming respective gate isolation layers that are thicker than the insulating layer of the capacitor, the thicknesses being measured in a direction (N) perpendicular to the surface of the substrate. 
   
   
       19 . The process according to  claim 13 , further comprising, with respect to a fourth portion of the substrate located on one side of the first portion corresponding to the second electrode of the capacitor opposite to the second portion of the substrate corresponding to the drift-field drain region, an extension under the insulating layer of the capacitor, said extension being doped at the same time as the second portion of the substrate. 
   
   
       20 . The process according to  claim 19 , further comprising doping the fourth portion of the substrate at the same time as source and drain regions of MOS transistors contained within the circuit. 
   
   
       21 . The process according to  claim 13 , further comprising forming portions of a silicide material on the first electrode of the capacitor, on the gate and on the source region of the transistor, by using a mask covering the substrate at least within a region extending between said first electrode and said gate in the longitudinal direction.