Maintaining Error Statistics Concurrently Across Multiple Memory Ranks

Abstract

A method and apparatus to maintain memory read error information concurrently across multiple ranks in a computer memory. An error detection unit associates a read error with a particular rank and with a particular chip in the rank. The error detection unit reports the error and the associated rank ID and chip ID to an error logging unit. The error logging unit maintains, for each rank ID and chip ID for which an error has been detected, a total number of errors that occur. A memory controller uses a fault pattern in the error logging unit to replace failing memory chips or memory ranks with a spare memory chip or a spare memory rank.

1 . A computer system comprising:
 a processor;   a memory further comprising a plurality of memory ranks coupled to the memory controller, each memory rank further comprising a plurality of memory chips;   an error detection unit configured to detect an error in data read from the memory and identifying a rank ID and a chip ID associated with the error; and   a memory controller coupled to the processor and to the memory, the memory controller configured to concurrently maintain error information for multiple memory ranks in the plurality of memory ranks.   
     
     
         2 . The computer system of  claim 1 , the memory controller further comprising:
 an error location list further comprising an error list item for each rank ID and chip ID combination for which an error has been detected by the error detection unit; and   an error counter bank configured to maintain an error count indicating how many times an error has been detected by the error detection unit for each rank ID and chip ID combination in the error location list.   
     
     
         3 . The computer system of  claim 2  wherein the error location list is configured as a content addressable memory. 
     
     
         4 . The computer system of  claim 2 , the memory controller configured to examine the error location list to detect a fault pattern and to use a spare memory chip or a spare memory rank responsive to the fault pattern. 
     
     
         5 . The computer system of  claim 4 , the fault pattern comprising an error in a particular chip for each memory rank in the plurality of memory ranks, the memory controller configured to use a spare memory chip in the plurality of memory ranks instead of the particular memory chip. 
     
     
         6 . The computer system of  claim 4 , the fault pattern comprising an error in every memory chip in a particular memory rank, the memory controller configured to use a spare memory rank instead of the particular memory rank. 
     
     
         7 . The computer system of  claim 4 , the fault pattern comprising a particular memory rank and memory chip combination having more than a specified number of errors, the memory controller configured to force a scrub of the particular memory rank, reset the error counter for the particular memory rank and memory chip combination, and set a flag that a scrub was performed on the particular memory rank; if, subsequently, the particular memory rank and memory chip combination again has more than the specified number of errors, the memory controller configured to then use a spare memory chip on the same memory rank, or to use a spare memory rank instead of the particular memory rank. 
     
     
         8 . The computer system of  claim 1  wherein the error detection unit is an error checking and correction unit. 
     
     
         9 . The computer system of  claim 1 , wherein the data read from the memory is read during a scrub read. 
     
     
         10 . The computer system of  claim 1 , wherein the data read from the memory is read during a functional read. 
     
     
         11 . A method performed by a computer system having a memory controller coupled to a memory further comprising a plurality of memory ranks, each memory rank further comprising a plurality of memory chips, including one or more spare memory chips, the method comprising:
 concurrently maintaining an error count for each memory rank and memory chip combination in the memory that has encountered an error;   analyzing the concurrently maintained error count for each memory rank and memory chip combination that has encountered an error to determine a fault pattern; and   using the fault pattern to improve reliability of the memory by using the one or more spare memory chips.   
     
     
         12 . The method of  claim 11 , wherein the fault pattern comprises an error for a corresponding memory chip in each memory rank in the plurality of memory ranks. 
     
     
         13 . The method of  claim 11 , wherein the fault pattern comprises an error for every memory chip in a particular memory rank in the plurality of memory ranks. 
     
     
         14 . The method of  claim 11 , further comprising:
 detecting an error in data read from the memory;   determining a rank ID and a chip ID combination associated with the error;   associating an error counter with the rank ID and chip ID combination associated with the error; and   incrementing the error counter associated with the rank ID and chip ID combination.   
     
     
         15 . The method of  claim 14 , further comprising:
 storing the rank ID and chip ID combination associated with the error in a content addressable memory (CAM).   
     
     
         16 . The method of  claim 14 , associating the error counter with the rank ID and chip ID combination associated with the error comprises iterating through an error location list to match the rank ID and chip ID combination associated with the error with a rank ID and chip ID combination stored in the error location list. 
     
     
         17 . The method of  claim 14 , associating the error counter with the rank ID and chip ID combination associated with the error comprises a parallel compare of the rank ID and the chip ID combination associated with the error with one or more rank ID and chip ID combinations stored in the error location list. 
     
     
         18 . The method of  claim 11 , further comprising resetting of the error count for each rank ID and chip ID combination at specified intervals. 
     
     
         19 . The method of  claim 11 , further comprising:
 if the error count for a particular rank ID and chip ID combination exceeds a specified value, then
 forcing a scrub of a particular memory rank identified by the particular rank ID; 
 resetting the error count for the particular rank ID and chip ID; and 
 setting a flag that the particular memory rank was scrubbed; and 
   if the error count for the particular rank ID and chip ID combination exceeds the specified value and the flag for the particular rank is set, then using a spare memory chip or a spare memory rank to replace the particular memory rank or a particular memory chip identified by the particular rank ID and chip ID combination.   
     
     
         20 . The method of  claim 19 , further comprising copying data from the particular memory rank or particular memory chip identified by the particular chip ID and rank ID combination to the spare memory chip or spare memory rank.