Semiconductor memory

Abstract

A SRAM memory is composed of FD-SOI transistors, and performance of the memory cell is improved by controlling an electric potential of a layer under a buried oxide film of a SOI transistor constituting a driver transistor. Performance of the SRAM circuit in the low power voltage state is improved. In the SRAM memory cell composed of the FD-SOI transistor, an electric potential of a well under a BOX layer is controlled to control a threshold voltage Vth, thereby increasing a current. Thus, the operations of the memory cell can be stabilized.

1 . A semiconductor memory including a static type memory cell comprising:
 a plurality of transistors each having an FD-SOI structure in which a SOI layer is completely depleted;   first and second storage nodes for storing therein data; and   a driver transistor using the transistors;   wherein said driver transistor comprises a semiconductor layer including a well layer formed in a semiconductor substrate and a buried oxide film layer provided in contact with said well layer;   a source node of said driver transistor is connected to a ground potential line; and   a gate node of said driver transistor is connected to said well layer.   
     
     
         2 . The semiconductor memory according to  claim 1 , wherein said well layer penetrates said semiconductor layer including said buried oxide film and is connected to a gate node via a contact provided under said gate node. 
     
     
         3 . The semiconductor memory according to  claim 2 , wherein the contact connected to said well layer is disposed at a position connects said gate node to metallic wiring provided via an inter-layer film on said gate node. 
     
     
         4 . A semiconductor memory including a static type memory cell comprising:
 a plurality of transistors each having an FD-SOI structure in which a SOI layer is completely depleted;   first and second storage nodes for storing therein data;   a driver transistor using the transistors; and   a bit line for access to a memory;   wherein said plurality of transistors are six transistors consisting of:   a pair of n-channel type of transfer transistors connected each to between said first and second storage nodes;   a pair of n-channel type of driver transistors each with a source node thereof connected to a ground potential line; and   a pair of p-channel type of load transistors each with a source node thereof connected to a first power line having an electric potential higher than the ground potential in said ground potential line.   
     
     
         5 . The semiconductor memory according to  claim 4 , wherein, in said static type memory cell, respective gate nodes of the driver transistor and load transistor are formed along the same straight line, and a contact connected to a well layer of said driver transistor is connected to said gate node disposed between said driver transistor and said load transistor so as to reach said well layer. 
     
     
         6 . The semiconductor memory according to  claim 4 , wherein the gates of said driver transistor and transfer transistor have the same design width. 
     
     
         7 . The semiconductor memory according to  claim 4 , wherein, in said static type memory cell, a voltage corresponding to a high electric potential of a word line connected to the gate node of said transfer transistor is higher than that corresponding to a high electric potential of a bit line for access to the memory cell. 
     
     
         8 . The semiconductor memory according to  claim 4 , wherein, in said static type memory cell, an electric potential of a first power line connected to the source node of said load transistor is higher than a voltage corresponding to a high electric potential of the bit line for access to the memory cell. 
     
     
         9 . The semiconductor memory according to  claim 4 , wherein the electric potential of said first power line is controlled to a level higher than the high electric potential state of the bit line while the memory circuit is being accessed, and to a level equal to the high electric potential state of the bit line while the memory circuit is not being accessed. 
     
     
         10 . The semiconductor memory according to  claim 4 , wherein, in said static type memory cell, a voltage corresponding to the high electric potential state of a word line connected to a gate node of said transfer transistor is equal to an electric potential_of a first power line connected to a source node of said load transistor and is higher than a voltage corresponding to the high electric potential state of a bit line for access to the memory cell. 
     
     
         11 . The semiconductor memory according to  claim 4 , wherein, in said static type of memory cell, a well layer of said load transistor is connected to a gate node of said load transistor. 
     
     
         12 . The semiconductor memory according to  claim 11 , wherein, in said static type memory cell, said load transistor with the gate node connected thereto and the well layer of said load transistor are formed integral with each other. 
     
     
         13 . The semiconductor memory according to  claim 12 , wherein, in said static type memory cell, respective gates of the driver transistor and the load transistor with said gate node connected thereto are formed along the same straight line, and a contact connected to the well formed in the integrated state is formed under the contact for connecting said gate node to said metallic wiring. 
     
     
         14 . The semiconductor memory according to  claim 11 , wherein, in said static type of memory cell, a voltage corresponding to the high electric potential state of a word line connected to the gate node of said transfer transistor is higher than a voltage corresponding to the high electric potential state of a bit line for access to the memory cell. 
     
     
         15 . The semiconductor memory according to  claim 4 , wherein, in said static type of memory cell, a well layer of said load transistor is connected to a first power line. 
     
     
         16 . The semiconductor memory according to  claim 15 , wherein, in said static type of memory cell, a voltage corresponding to the high electric potential state of a word line connected to a gate node of said transfer transistor is equal to an electric potential of a first power line connected to a source node of said load transistor and is higher than a voltage corresponding to the high electric potential state of a bit line for access to the memory cell. 
     
     
         17 . The semiconductor memory according to  claim 4 , wherein, in said static type of memory cell, a well layer of said transfer transistor is connected to a word line as a gate node of said transfer transistor. 
     
     
         18 . The semiconductor memory according to  claim 17 , wherein, in said static type of memory cell, an electric potential of a first power line connected to a source node of said load transistor is higher than a voltage corresponding to the high electric potential state of a bit line for access to the memory cell. 
     
     
         19 . The semiconductor memory according to  claim 17 , wherein, in said static type of memory cell, a well layer of said load transistor is connected to a gate node of said load transistor. 
     
     
         20 . The semiconductor memory according to  claim 19 , wherein, in said static type of memory cell, a voltage corresponding to the high electric potential state of a word line connected to a gate node of said transfer transistor is equal to an electric potential of a first power line connected to a source node of said load transistor and is higher than a voltage corresponding to a high electric potential of a bit line for access to the memory cell. 
     
     
         21 . The semiconductor memory according to  claim 4 , wherein, in said static type of memory cell, a well layer of said transfer transistor is connected to a storage node connected to a source node of said transfer transistor. 
     
     
         22 . The semiconductor memory according to  claim 21 , wherein, in said static type of memory cell, a well layer of said load transistor is connected to a gate node of said load transistor. 
     
     
         23 . The semiconductor memory according to  claim 21 , wherein, in said static type of memory cell, a voltage corresponding to the high electric potential state of a word line connected to a gate node of said transfer transistor is higher than a voltage corresponding to the high electric potential state of a bit line for access to the memory cell. 
     
     
         24 . The semiconductor memory according to  claim 24 , wherein, in said static type of memory cell, a well layer of said transfer transistor is connected to a first power line connected to a source node of said load transistor. 
     
     
         25 . The semiconductor memory according to  claim 24 , wherein, in said static type of memory cell, a voltage corresponding to a low electric potential state of a word line connected to a gate node of said transfer transistor is lower than a ground electric potential of 0 V. 
     
     
         26 . The semiconductor memory according to  claim 24 , wherein, in said static type of memory cell, a source line SL for said driver transistor is connected between memory cells sharing a common word line; and said source line SL is control to the ground electric potential of 0V in the high electric potential state of the word line and to a voltage higher than the ground electric potential in the low electric potential state of said word line. 
     
     
         27 - 31 . (canceled) 
     
     
         32 . The semiconductor memory according to  claim 2 , wherein a gate node and a well node under a buried oxide film are connected to a transistor forming a logic circuit mounted together with said static type of memory cell on the same semiconductor substrate. 
     
     
         33 . The semiconductor memory according to  2 , wherein said 6-transistor memory cell and 4-transistor memory sell are formed on the same substrate.