Semiconductor structure with field shield and method of forming the structure

Abstract

Disclosed is semiconductor structure that incorporates a field shield below a semiconductor device (e.g., a field effect transistor (FET) or a diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the device (e.g., a source/drain region of a FET or a cathode or anode of a diode). Current that passes into the device, for example, during back-end of the line charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below. This field shield further provides a protective barrier against any electric charge that becomes trapped within the lower isolation layer or substrate

1 . A semiconductor structure comprising:
 a substrate;   a first isolation layer on said substrate;   a conductive pad on said first isolation layer;   a second isolation layer on said conductive pad; and   a device, having a doped semiconductor region, on said second isolation layer, wherein said conductive pad is electrically coupled to said doped semiconductor region and electrically isolated from said substrate.   
   
   
       2 . The semiconductor structure of  claim 1 , further comprising a conductor that is adjacent to said doped semiconductor region, that extends vertically through said second isolation layer to said conductive pad and that electrically couples said conductive pad to said doped semiconductor region. 
   
   
       3 . The semiconductor structure of  claim 1 , wherein said device comprises a field effect transistor and wherein said doped semiconductor region comprises a source/drain region of said field effect transistor. 
   
   
       4 . The semiconductor structure of  claim 1 , wherein said device comprises a diode and wherein said doped semiconductor region comprises one of an anode and a cathode of said diode. 
   
   
       5 . The semiconductor structure of  claim 2 , wherein said conductive pad and said conductor each comprise one of a doped polysilicon and a conductive metal. 
   
   
       6 . The semiconductor structure of  claim 2 , further comprising a metal strap adjacent to said conductor and said doped semiconductor region. 
   
   
       7 . A semiconductor structure comprising:
 a substrate;   a first isolation layer on said substrate;   a conductive pad on said first isolation layer;   a second isolation layer on said conductive pad; and   a field effect transistor, having source/drain regions, on said second isolation layer, wherein said conductive pad is electrically coupled to one of said source/drain regions and electrically isolated from said substrate.   
   
   
       8 . The semiconductor structure of  claim 7 , further comprising a conductor that is adjacent to said one of said source/drain regions, that extends vertically through said second isolation layer to said conductive pad and that electrically couples said conductive pad to said one of said source/drain regions. 
   
   
       9 . The semiconductor structure of  claim 7 , wherein said conductive pad and said conductor each comprise one of a doped polysilicon and a conductive metal. 
   
   
       10 . The semiconductor structure of  claim 7 , further comprising a metal strap adjacent to said conductor and said one of said source/drain regions. 
   
   
       11 . A method of forming a semiconductor structure, said method comprising:
 providing a wafer comprising a substrate, a first isolation layer on said substrate, a conductive layer on said first isolation layer, a second isolation layer on said conductive layer and a semiconductor layer on said second isolation layer;   etching a trench in said wafer through said semiconductor layer to said first isolation layer so as to form a stack on said first isolation layer;   forming a spacer adjacent to a sidewall of said stack;   after said forming of said spacer, filling said trench with a dielectric material;   selectively removing said spacer to create an opening adjacent to said sidewall;   depositing a conductor into said opening; and   forming a semiconductor device above said second isolation layer, wherein said forming of said semiconductor device comprises forming, adjacent to said conductor, a doped semiconductor region.   
   
   
       12 . The method of  claim 11 , wherein said forming of said semiconductor device comprises forming a field effect transistor and wherein said forming of said doped semiconductor region comprises forming, within said semiconductor layer, source/drain regions such that one of said source/drain regions is adjacent to said conductor. 
   
   
       13 . The method of  claim 11 , wherein said forming of said semiconductor device comprises forming a diode and wherein said forming of said doped semiconductor region comprises forming, within said semiconductor layer, an anode and a cathode such that one of said anode and said cathode is adjacent to said conductor. 
   
   
       14 . The method of  claim 11 , further comprising forming a metal strap connecting said conductor and said doped semiconductor region. 
   
   
       15 . A method of forming a semiconductor structure, said method comprising:
 providing a wafer comprising a substrate, a first isolation layer on said substrate, a conductive layer on said first isolation layer, a second isolation layer on said conductive layer and a semiconductor layer on said second isolation layer;   etching a trench in said wafer through said semiconductor layer to said first isolation layer so as to form a stack on said first isolation layer;   forming a spacer adjacent to a sidewall of said stack, wherein said spacer comprises a conductor;   after said forming of said spacer, filling said trench with a dielectric material; and   forming a device above said second isolation layer, wherein said forming of said device comprises forming, adjacent to said conductor, a doped semiconductor region.   
   
   
       16 . The method of  claim 15 , wherein said forming of said device comprises forming a field effect transistor and wherein said forming of said doped semiconductor region comprises forming, within said semiconductor layer, source/drain regions such that one of said source/drain regions is adjacent to said conductor. 
   
   
       17 . The method of  claim 15 , wherein said forming of said device comprises forming a diode and wherein said forming of said doped semiconductor region comprises forming, within said semiconductor layer, an anode and a cathode such that one of said anode and said cathode is adjacent to said conductor. 
   
   
       18 . The method of  claim 15 , further comprising forming a metal strap adjacent to said conductor and said doped semiconductor region.