Method for clamping a semiconductor region at or near ground

Abstract

A clamping circuit clamps a voltage received by an n-type semiconductor region without using a Schottky transistor. The clamping circuit includes a current mirror as well as first and second bipolar transistors. The current mirror receives a first current and supplies a second current in response. The first current is received by the first bipolar transistor, and the second current is received by the second bipolar transistor. The difference between the base-emitter junction voltages of the first and second bipolar transistors, in part, defines the voltage at which the n-type region is clamped. To start-up the circuit properly, current is withdrawn from the base/gate terminals of the transistors disposed in the current mirror. The circuit optionally includes a pair of cross-coupled transistors to reduce the output impedance and improve the power supply rejection ratio.

1 . A circuit adapted to control a clamping voltage of a semiconductor region formed in a semiconductor substrate, the circuit comprising:
 a current mirror receiving a first current and supplying a second current in response;   a first transistor adapted to generate a first voltage in accordance with the first current; and   a second transistor adapted to generate a second voltage in accordance with the second current; wherein said clamping voltage is defined by a difference of said first and second voltages.   
   
   
       2 . The circuit of  claim 1  wherein said first and second transistors are bipolar transistors, and said first and second voltages are base-emitter voltages. 
   
   
       3 . The circuit of  claim 1  wherein said first and second transistors are MOS transistors, and said first and second voltages are gate-source voltages. 
   
   
       4 . The circuit of  claim 2  wherein said first bipolar transistor is a NPN transistor having an emitter terminal coupled to the semiconductor region, and wherein said second bipolar transistor is an NPN transistor having an emitter terminal coupled to a ground terminal. 
   
   
       5 . The circuit of  claim 4  wherein said current mirror comprises:
 a third bipolar transistor having an emitter terminal coupled to a first supply voltage, and a collector terminal coupled to the collector terminal of the first NPN transistor; and   a fourth bipolar transistor having an emitter terminal coupled to the first supply voltage, a collector terminal coupled to the collector terminal of the second NPN transistor, and a base terminal coupled to the base terminal of the third bipolar transistor.   
   
   
       6 . The circuit of  claim 4  wherein said current mirror comprises:
 a first MOS transistor having a source terminal coupled to a first supply voltage, and a drain terminal coupled to the collector terminal of the first NPN transistor; and   a second MOS transistor having a source terminal coupled to the first supply voltage, a drain terminal coupled to the collector terminal of the second NPN transistor, and a gate terminal coupled to the gate terminal of the third bipolar transistor.   
   
   
       7 . The circuit of  claim 5  further comprising:
 a fifth bipolar transistor having a base terminal coupled to the emitter terminal of the second transistor, an emitter terminal coupled to the semiconductor region and a collector terminal coupled to the base terminal of the third transistor.   
   
   
       8 . The circuit of  claim 7  further comprising:
 a resistive element coupled to the semiconductor region.   
   
   
       9 . A method of controlling a clamping voltage of a semiconductor region formed in a semiconductor substrate, the method comprising:
 causing a first voltage to be supplied in accordance with a first current;   causing a second voltage to be supplied in accordance with a second current; and   applying a voltage defined by a difference of said first and second voltages between the semiconductor region and a ground terminal.   
   
   
       10 . The method of  claim 9  wherein said first voltage is caused to be supplied across a first base-emitter junction formed in a first bipolar transistor, and wherein said second voltage is caused to be supplied across a second base-emitter junction formed in a second bipolar transistor. 
   
   
       11 . The method of  claim 9  wherein said first voltage is caused to be supplied across a first gate-to-source junction of a first MOS transistor, and wherein said second voltage is caused to be supplied across a gate-to-source junction of a second bipolar transistor. 
   
   
       12 . The method of  claim 10  wherein said first current is supplied by a third bipolar transistor and wherein said second current is supplied by a fourth bipolar transistor, the method further comprising:
 drawing current from base terminals of the first and second bipolar transistors during a start-up phase.   
   
   
       13 . The method of  claim 10  wherein said first current is supplied by a first MOS transistor and wherein said second current is supplied by a second MOS transistor, the method further comprising:
 drawing current from gate terminals of the first and second MOS transistors during a start-up phase.   
   
   
       14 . A circuit adapted to control a clamping voltage of a semiconductor region formed in a semiconductor substrate, the circuit comprising:
 a current mirror receiving a first current and supplying a second current in response;   a first transistor adapted to generate a first voltage in accordance with the first current;   a second transistor adapted to generate a second voltage in accordance with the second current; and   a cross-coupled transistor pair having disposed therein a third transistor adapted to generate a third voltage in accordance with the first current and a fourth transistor adapted to generate a fourth voltage in accordance with the second current; wherein said clamping voltage is defined by a difference of a sum of said first and fourth voltages and a sum of said second and third voltages.   
   
   
       15 . The circuit of  claim 14  wherein said first, second, third and fourth transistors are bipolar transistors, and said first, second, third and fourth voltages are base-emitter voltages. 
   
   
       16 . The circuit of  claim 14  wherein said first, second, third and fourth transistors are MOS transistor, and said first, second, third and fourth voltages are gate-to-source voltages. 
   
   
       17 . The circuit of  claim 14  wherein said first, second, third and fourth transistors are bipolar NPN transistors, wherein an emitter terminal of the first transistor is coupled to a base terminal of the fourth transistor and to a collector terminal of the third transistor, wherein an emitter terminal of the second transistor is coupled to a base terminal of the third transistor and to a collector terminal of the fourth transistor, wherein an emitter terminal of the fourth transistor is coupled to the semiconductor region and wherein an emitter terminal of the third transistor is coupled to the ground terminal. 
   
   
       18 . The circuit of  claim 17  wherein said current mirror comprises:
 a fifth bipolar transistor having an emitter terminal coupled to a first supply voltage, a collector terminal coupled to collector and base terminals of the first bipolar transistor; and   a sixth bipolar transistor having an emitter terminal coupled to the first supply voltage, a collector terminal coupled to the collector terminal of the second bipolar transistor, and a base terminal coupled to the base terminal of the fifth bipolar transistor and to a collector terminal of the second bipolar transistor.   
   
   
       19 . The circuit of  claim 18  further comprising:
 a current source adapted to supply a current to collector terminals of the first and fifth bipolar transistors.   
   
   
       20 . The circuit of  claim 19  further comprising:
 a resistive element coupled to the semiconductor region.   
   
   
       21 . A method of controlling a clamping voltage of a semiconductor region formed in a semiconductor substrate, the method comprising:
 causing first and second voltages to be supplied in accordance with a first current;   causing third and fourth voltages to be supplied in accordance with a second current;   generating a fifth voltage defined by a difference of a sum of said first and fourth voltages and a sum of said second and third voltages; and   applying the fifth voltage between the semiconductor region and a ground terminal.   
   
   
       22 . The method of  claim 21  wherein said first and second, third and fourth voltages are base-emitter voltages of first, second, third and fourth bipolar transistors respectively. 
   
   
       23 . The method of  claim 21  wherein said first, second, third and fourth voltages are gate-to-source voltages of first, second, third and fourth MOS transistors respectively. 
   
   
       24 . The method of  claim 21  wherein said first current is supplied by a third bipolar transistor and wherein said second current is supplied by a fourth bipolar transistor, the method further comprising:
 supplying a current to a terminal of the third bipolar transistor during a start-up phase.   
   
   
       25 . The method of  claim 21  wherein said first current is supplied by a first MOS transistor and wherein said second current is supplied by a second MOS transistor, the method further comprising:
 supplying a current to a terminal of the first MOS transistor during a start-up phase.   
   
   
       26 . A circuit adapted to control a clamping voltage of a semiconductor region formed in a semiconductor substrate, the circuit comprising:
 a first transistor adapted to supply a first voltage in accordance with a first current;   a second transistor adapted to supply a second voltage in accordance with a second current; and   a cross-coupled transistor pair having a third transistor adapted to supply a third voltage in accordance with the first current, and a fourth transistor adapted to supply a fourth voltage in accordance with the second current; wherein said clamping voltage is defined by a difference of a sum of the second and third voltages and a sum of said first and fourth voltages.   
   
   
       27 . The circuit of  claim 26  wherein said first, second, third and fourth voltages are base-emitter voltages of first, second, third and fourth bipolar transistors. 
   
   
       28 . The circuit of  claim 26  wherein said first, second, third and fourth voltages are gate-to-source voltages of first, second, third and fourth MOS transistors. 
   
   
       29 . The circuit of  claim 27  wherein said first, second, third and fourth transistors are bipolar NPN transistors, wherein an emitter terminal of the first transistor is coupled to the base terminal of the fourth transistor and to a collector terminal of the third transistor, wherein an emitter terminal of the second transistor is coupled to the base terminal of the third transistor and to a collector terminal of the fourth transistor, wherein an emitter terminal of the fourth transistor is coupled to the semiconductor region and wherein an emitter terminal of the third transistor is coupled to a ground terminal. 
   
   
       30 . The circuit of  claim 29  wherein said circuit further comprises:
 a fifth transistor having a first terminal coupled to a first supply voltage, and a second terminal coupled to the collector and base terminals of the first bipolar NPN transistor;   a sixth transistor having a first terminal coupled to the first supply voltage, and second and third terminals coupled to a third terminal of the fifth transistor; and   a seventh transistor having a first terminal coupled to the second terminal of the sixth transistor, a second terminal coupled to the base terminal of the fourth transistor, and a third terminal coupled to the ground terminal.   
   
   
       31 . The circuit of  claim 30  wherein said fifth and sixth transistors are bipolar PNP transistors. 
   
   
       32 . The circuit of  claim 30  wherein said fifth and sixth transistors are PMOS transistors. 
   
   
       33 . The circuit of  claim 31  wherein said circuit further comprises:
 an eight bipolar NPN transistor having a collector terminal coupled to the collector terminal of the seventh transistor, a base terminal coupled to the ground terminal, and an emitter terminal coupled to the semiconductor region.   
   
   
       34 . A method of controlling a clamping voltage of a semiconductor region formed in a semiconductor substrate, the method comprising:
 causing first and second voltages to be supplied in accordance with a first current;   causing third and fourth voltages to be supplied in accordance with a second current;   developing a fifth voltage defined by a difference of a sum of said second and third voltages and a sum of said first and fourth voltages;   applying the fifth developed voltage across the semiconductor region and a ground terminal; and   withdrawing current from said first and second transistors during a start-up phase.   
   
   
       35 . The method of  claim 34  wherein said first and second voltages are base-emitter voltages of first and second bipolar transistors respectively. 
   
   
       36 . The method of  claim 34  wherein said first and second voltages are gate-to-source voltages of first and second MOS transistors respectively. 
   
   
       37 . A circuit adapted to control a clamping voltage of a semiconductor region formed in a semiconductor substrate, the circuit comprising:
 a first bipolar transistor having an emitter terminal coupled to the semiconductor region, wherein a biasing voltage applied to the first transistor is in part proportional to a current flowing through the first transistor.   
   
   
       38 . The circuit of  claim 37  further comprising:
 a second bipolar transistor flowing a current that is proportional to the current flowing through the first transistor.