Non-Volatile Memory Device and Method for Manufacturing the Same

Abstract

An increase of charge storing capacity, prevention of an over-erase, and a reduction of ΔVth may be achieved when a 2-bit/cell non-volatile memory device includes a gate of a predetermined width above a semiconductor substrate, an insulating layer between the gate and the semiconductor substrate and at lateral sides of the gate, having a greater width than the gate, a pair of storage layers at the lateral sides of the gate, a pair of blocking layers at the lateral sides of the gate and covering the pair of storage layers, a source and a drain formed in the semiconductor substrate at first opposed locations external to the gate, and a trap impurity implanted into the insulating layer at second locations external to the gate.

1 . A non-volatile memory device, comprising:
 a gate of a predetermined width above a semiconductor substrate;   an insulating layer between the gate and the semiconductor substrate and at lateral sides of the gate, having a greater width than that of the gate;   a pair of storage layers at lateral sides of the gate;   a pair of blocking layers at the lateral sides of the gate and covering the pair of storage layers;   a source and a drain in the semiconductor substrate at first locations external to the gate; and   a trap impurity in the insulating layer at second locations external to the gate.   
   
   
       2 . The non-volatile memory device of  claim 1 , wherein the trap impurity is near an interface of the semiconductor substrate with the insulating layer. 
   
   
       3 . The non-volatile memory device of  claim 2 , wherein the trap impurity has a maximum concentration closer to the interface of the semiconductor substrate with the insulating layer than to an upper surface of the insulating layer. 
   
   
       4 . The non-volatile memory device of  claim 1 , wherein the trap impurity comprises nitrogen, germanium, and/or oxygen. 
   
   
       5 . The non-volatile memory device of  claim 4 , wherein the trap impurity comprises a combination of nitrogen, germanium, and/or oxygen. 
   
   
       6 . The non-volatile memory device of  claim 4 , wherein the insulating layer and the blocking layer each independently comprise an oxide layer, and the storage layer comprises a nitride. 
   
   
       7 . The non-volatile memory device of  claim 6 , wherein the trap impurity comprises nitrogen, the nitrogen having a concentration of about 10 22  atoms/cm 3 . 
   
   
       8 . The non-volatile memory device of  claim 1 , wherein the insulating layer and the blocking layer each independently comprise an oxide layer, and the storage layer comprises a nitride. 
   
   
       9 . The non-volatile memory device of  claim 8 , wherein the storage layer comprises silicon nitride. 
   
   
       10 . The non-volatile memory device of  claim 1 , wherein each of the storage layers is capable of independently storing a bit of data. 
   
   
       11 . The non-volatile memory device of  claim 1 , wherein the source and drain are substantially aligned with external sidewalls of the pair of storage layers. 
   
   
       12 . The non-volatile memory device of  claim 1 , wherein the insulating layer comprises a bottom insulating layer. 
   
   
       13 . The non-volatile memory device of  claim 12 , wherein the bottom insulating layer comprises an oxide. 
   
   
       14 . The non-volatile memory device of  claim 1 , further comprising a side wall insulating layer on the gate. 
   
   
       15 . The non-volatile memory device of  claim 14 , wherein the side wall insulating layer comprises an oxide. 
   
   
       16 . The non-volatile memory device of  claim 15 , wherein the side wall insulating layer comprises silicon oxide doped with fluorine, boron, and/or phosphorous. 
   
   
       17 . The non-volatile memory device of  claim 15 , wherein the side wall insulating layer comprises undoped silicon oxide. 
   
   
       18 . The non-volatile memory device of  claim 1 , wherein the device comprises trap sites, the trap sites having the trap impurity. 
   
   
       19 . The non-volatile memory device of  claim 1 , wherein a height of the storage layer is less than a height of the gate. 
   
   
       20 . The non-volatile memory device of  claim 1 , wherein the device is a SONOS device.