Nonvolatile memory device and method of manufacturing the same

Abstract

The nonvolatile memory device includes a semiconductor substrate, and a device isolation layer defining an active region in the semiconductor substrate. The device isolation layer includes a top surface lower than a top surface of the semiconductor substrate, such that a side-upper surface of the active region is exposed. A sense line crosses both the active region and the device isolation layer, and a word line, spaced apart from the sense line, crosses both the active region and the device isolation layer.

1 . A nonvolatile memory device comprising:
 a semiconductor substrate;   at least one device isolation layer defining an active region in the semiconductor substrate, the device isolation layer including a top surface lower than a top surface of the semiconductor substrate, such that a side-upper surface of the active region is exposed;   a sense line crossing both the active region and the device isolation layer; and   a word line spaced apart from the sense line and crossing both the active region and the device isolation layer.   
   
   
       2 . The nonvolatile memory device of  claim 1 , wherein the word line comprises:
 a gate insulation layer on the semiconductor substrate; and   a gate electrode on the gate insulation layer.   
   
   
       3 . The nonvolatile memory device of  claim 2 , wherein the gate electrode disposed in the active region comprises a bottom surface higher than a bottom surface of the gate electrode disposed in the device isolation layer. 
   
   
       4 . The nonvolatile memory device of  claim 2 , wherein a bottom surface of the gate electrode disposed in the device isolation layer is lower than a top surface of the active region. 
   
   
       5 . The nonvolatile memory device of  claim 2 , wherein a portion of the gate electrode faces the exposed side-upper surface of the active region. 
   
   
       6 . The nonvolatile memory device of  claim 1 , wherein the sense line comprises:
 a tunnel insulation layer on the semiconductor substrate;   a floating gate on the tunnel insulation layer;   an inter-gate dielectric on the floating gate; and   a control gate on the inter-gate dielectric.   
   
   
       7 . The nonvolatile memory device of  claim 6 , wherein a bottom surface of the floating gate disposed in the active region is higher than a bottom surface of the floating gate disposed in the device isolation layer. 
   
   
       8 . The nonvolatile memory device of  claim 6 , wherein a portion of the floating gate faces the exposed side-upper surface of the active region. 
   
   
       9 . The nonvolatile memory device of  claim 6 , wherein a portion of the inter-gate dielectric and a portion of the control gate are lower than a top surface of the active region. 
   
   
       10 . The nonvolatile memory device of  claim 1 , wherein the active region comprises a top surface, a side surface, and a rounded edge where the top surface and the side surface cross each other. 
   
   
       11 . The nonvolatile memory device of  claim 10 , wherein the sense line and the word line cross the rounded edge. 
   
   
       12 . The nonvolatile memory device of  claim 1 , further comprising
 a pocket p-well on the semiconductor substrate, and   an n-well surrounding the pocket p-well on the semiconductor substrate.   
   
   
       13 . A nonvolatile memory device comprising:
 an active region in a semiconductor substrate, the active region having a top surface higher than a top surface of at least one neighboring device isolation layer; and   first and second transistor structures formed on the active region.   
   
   
       14 . The nonvolatile memory device of  claim 13 , wherein the top surface of the active region has a rounded edge. 
   
   
       15 . The nonvolatile memory device of  claim 14 , wherein the first transistor structure includes a portion of a word line and the second transistor structure includes a portion of a sense line. 
   
   
       16 . The nonvolatile memory device of  claim 14 , wherein a word line connects to the first transistor structure and a sense line connects to the second transistor structure. 
   
   
       17 . The nonvolatile memory device of  claim 13 , wherein the first transistor structure comprises:
 a gate insulation layer;   a first gate electrode;   a first inter-gate dielectric; and   a second gate electrode.   
   
   
       18 . The nonvolatile memory device of  claim 13 , wherein the second transistor structure comprises:
 a tunnel insulation layer;   a floating gate;   a second inter-gate dielectric; and   a control gate.   
   
   
       19 . A card, comprising:
 a nonvolatile memory including
 a semiconductor substrate, 
 at least one device isolation layer defining an active region in the semiconductor substrate, the device isolation layer including a top surface lower than a top surface of the semiconductor substrate, such that a side-upper surface of the active region is exposed, 
 a sense line crossing both the active region and the device isolation layer, and 
 a word line spaced apart from the sense line and crossing both the active region and the device isolation layer; and 
   a control unit configured to control the memory.   
   
   
       20 . The card of  claim 19 , wherein
 the active region comprises a top surface, a side surface, and a rounded edge where the top surface and the side surface cross each other, and   the sense line and the word line cross the rounded edge.