Semiconductor device with improved short channel effect of a pmos and stabilized current of an nmos and method for manufacturing the same

Abstract

The present invention relates to a semiconductor device which is capable of simultaneously improving a short channel effect of a PMOS and the current of an NMOS and a method for manufacturing the same. The semiconductor device includes first and second gates formed over first and second areas of a semiconductor substrate, respectively; and first and second junction areas formed in a portion of the semiconductor substrate corresponding to both sides of the first gate and a portion of the semiconductor substrate corresponding to both sides of the second gate, and including a projection, respectively, wherein the projection of the first junction area has a height higher than the height of the projection of the second junction area, and the second junction area is formed such that it has a depth from the surface of the semiconductor substrate deeper than the depth of the first junction area.

1 . A semiconductor device, comprising:
 first and second gates formed over first and second areas of a semiconductor substrate, respectively; and   first and second junction areas formed in a portion of the semiconductor substrate corresponding to both sides of the first gate and a portion of the semiconductor substrate corresponding to both sides of the second gate, and including a projection, respectively,   wherein the projection of the first junction area has a height higher than the height of the projection of the second junction area, and   the second junction area is formed to a depth from the surface of the semiconductor substrate deeper than the depth of the first junction area.   
   
   
       2 . The semiconductor device according to  claim 1 , wherein the first area is a PMOS area and the second area is an NMOS area. 
   
   
       3 . The semiconductor device according to  claim 1 , wherein the first and second gates are made in a structure including an N +  polysilicon layer. 
   
   
       4 . The semiconductor device according to  claim 1 , wherein the projections of the first and second junction areas are made of an epitaxial layer. 
   
   
       5 . The semiconductor device according to  claim 1 , wherein the epitaxial layer includes a SiGe layer. 
   
   
       6 . A method for manufacturing a semiconductor device, comprising the steps of:
 forming first and second gates over first and second areas of a semiconductor substrate, respectively;   selectively ion implanting impurities into the surface of the semiconductor substrate corresponding to both sides of the first gate;   growing first and second epitaxial layers over the portion of the semiconductor substrate corresponding to both sides of the first gate into which the impurities are ion implanted and a portion of the semiconductor substrate corresponding to both sides of the second gate, respectively, so as to have a higher height over the portion of the semiconductor substrate corresponding to both sides of the first gate into which the impurities are ion implanted; and   forming a first junction area in a portion of semiconductor substrate corresponding to both sides of the first gate including the first epitaxial layer and forming a second junction area, having a depth from a surface of the semiconductor substrate deeper than a depth of the first junction area, in a portion of semiconductor substrate corresponding to both sides of the second gate including the second epitaxial layer.   
   
   
       7 . The method according to  claim 6 , wherein the first area is a PMOS area and the second area is an NMOS area. 
   
   
       8 . The method according to  claim 6 , wherein the first and second gates are formed in a structure including an N +  polysilicon layer. 
   
   
       9 . The method according to  claim 6 , wherein the step of ion implanting selectively the impurities into the surface of the semiconductor substrate corresponding to both sides of the first gate is performed using P-type impurities. 
   
   
       10 . The method according to  claim 9 , wherein the P-type impurities include boron (B). 
   
   
       11 . The method according to  claim 6 , wherein the step of growing the epitaxial layer is performed through a selective epitaxial growth (SEG) process. 
   
   
       12 . The method according to  claim 6 , wherein the epitaxial layer is grown to a SiGe layer.