Integrated margin testing

Abstract

A margin testing system comprises a margin testing controller and a frequency control module. The margin testing controller is internal to and integrated with an electronic system under test and is coupled with a plurality of components that are configured to provide the functionality of the electronic system under test. The plurality of components includes a processor of the electronic system under test. The frequency control module is in communication with the margin testing controller. The frequency control module is configured for varying a clock frequency associated with at least one of the components for frequency margin testing the at least one of the components in response to command of the margin testing controller.

1 . A margin testing system comprising:
 a margin testing controller internal to and integrated with an electronic system under test and coupled with a plurality of components configured to provide functionality of said electronic system under test, wherein said plurality of components includes a processor of said electronic system under test; and   a frequency control module in communication with said margin testing controller, said frequency control module configured for varying a clock frequency associated with at least one of said components for frequency margin testing said at least one of said components in response to command of said margin testing controller.   
   
   
       2 . The margin testing system of  claim 1 , wherein said frequency control module comprises:
 a frequency synthesizer generating a clock signal at a selected frequency in response to command of said margin testing controller.   
   
   
       3 . The margin testing system of  claim 1 , further comprising:
 a voltage control module in communication with said margin testing controller, said voltage control module varying a voltage applied said at least one of said components for voltage margin testing of said at least one of said components in response to command of said margin testing controller; and   a fault bypass module in communication with said margin testing controller, said fault block module disabling selected automatic fault response mechanisms of said electronic system under test in response to command of said margin testing controller.   
   
   
       4 . The margin testing system of  claim 3 , wherein said voltage control module comprises:
 a digital potentiometer incorporated in a feedback circuit of a voltage regulator supplying voltage to said at least one of said components so as to adjust a resistance associated with said feedback circuit, thereby adjusting an output voltage of said regulator in response to command of said margin testing controller.   
   
   
       5 . The margin testing system of  claim 3 , further comprising:
 an external system in communication with said margin testing controller for transmitting an initiation command to said margin testing controller for initiating margin testing of one or more marginable components of said plurality of components.   
   
   
       6 . The margin testing system of  claim 3 , further comprising:
 a module for monitoring response of said electronic system under test to any of said clock frequency and said voltage variations.   
   
   
       7 . The margin testing system of  claim 1 , wherein said margin testing controller comprises:
 a Baseboard Management Controller (BMC).   
   
   
       8 . The margin testing system of  claim 7 , further comprising:
 an Inter-integrated Circuit-based bus providing communication between said BMC and said frequency and voltage control modules.   
   
   
       9 . The margin testing system of  claim 8 , wherein said Inter-integrated Circuit-based bus is an Intelligent Platform Management Bus (IPMB). 
   
   
       10 . The margin testing system of  claim 1 , wherein said electronic system under test comprises:
 a computer system.   
   
   
       11 . The margin testing system of  claim 10 , wherein said computer system comprises:
 a server employing an IPMI protocol   
   
   
       12 . The margin testing system of  claim 10 , wherein said at least one of said components comprises:
 front-side bus components of said computer system.   
   
   
       13 . The margin testing system of  claim 1 , wherein said at least one of said components comprises:
 said processor.   
   
   
       14 . The margin testing system of  claim 13 , wherein said processor comprises:
 a central processing unit of said electronic system under test.   
   
   
       15 . The margin testing system of  claim 1 , wherein said at least one of said components comprises:
 a memory module of said electronic system under test.