Circuit for providing automatic adaptation to frequency offsets in high speed serial links

Abstract

Aspects of providing automatic adaptation to frequency offsets in high speed serial links are described. First signals for phase adjusts in a receiver link are adjusted by detecting trends in the first signals to generate second signals, the second signals improving a rate of compensation for the frequency offsets by the phase adjusts. An up/down counter is included for counting signals for phase adjustments by a clock-data-recovery loop of a serial receiver. An adder is coupled to the up/down counter and outputs accumulated data indicative of a trend in the phase adjustments. Combinatorial logic coupled to the adder adapts the signals based on the accumulated data.

1 . A circuit comprising:
 a controller that generates first rotate up and rotate down signals for phase adjusts in a receiver link to adapt to frequency offsets, the first rotate up and rotate down signals causing rotation of a phase of a clock signal up or down to compensate for the frequency offsets; and   an adjust circuit coupled to the controller, the adjust circuit detecting trends in the first rotate up and rotate down signals and using combinatorial logic to adapt the first rotate up and rotate down signals for the phase adjusts based on accumulated data accumulated by an adder by generating second rotate up and rotate down signals improving a rate of compensation for the frequency offsets by the phase adjusts, the improvement relative to the compensation provided by using only the first rotate up and rotate down signals for adapting to the frequency offsets, and wherein the first rotate up and rotate down signals and the second rotate up and rotate down signals are logically ORed to provide the phase adjusts of the clock signal.   
   
   
       2 . The circuit of  claim 1  wherein the adjust circuit monitors for an overflow of the first rotate up and rotate down signals. 
   
   
       3 . The circuit of  claim 2  wherein the adjust circuit monitors for an overflow by counting and accumulating the first rotate up and rotate down signals. 
   
   
       4 . The circuit of  claim 2  wherein the adjust circuit monitors for an overflow with an up/down counter coupled to the adder. 
   
   
       5 . The circuit of  claim 4  wherein the adjust circuit generates the second rotate up and rotate down signals by detecting overflow and underflow in the adder and logically combining the overflow and underflow with the first rotate up and rotate down signals by the combinatorial logic. 
   
   
       6 . A circuit comprising:
 an up/down counter for counting rotate up and rotate down signals from a phase rotator control for phase adjustments by a clock-data-recovery loop of a serial receiver;   an adder coupled to the up/down counter that outputs accumulated data indicative of a trend in the phase adjustments; and   combinatorial logic coupled to the adder to adapt the rotate up and rotate down signals based on the accumulated data, wherein the combinatorial logic generates a new rotate up signal based on an overflow in the adder and wherein the combinatorial logic generates a new rotate down signal based on an underflow in the adder.   
   
   
       7 . The circuit of  claim 6  wherein the adder accumulates a chosen number of most significant bits of the up/down counter. 
   
   
       8 . The circuit of  claim 6  wherein the rotate up and rotate down signals are for phase adjusts in a receiver link to adapt to frequency offsets and causing rotation of a phase of a clock signal up or down to compensate for the frequency offsets, and wherein the new rotate up and rotate down signals improve a rate of compensation for the frequency offsets by the phase adjusts, the improvement relative to the compensation provided by using only the rotate up and rotate down signals for adapting to the frequency offsets, and wherein the rotate up and rotate down signals and the new rotate up and rotate down signals are logically ORed to provide the phase adjusts. 
   
   
       9 . A circuit comprising:
 an adjust circuit that monitors trends of phase adjusts of signals, including using an up/down counter and adder to accumulate phase adjust data from the phase adjusts, wherein the phase adjusts include first rotate up and rotate down signals for phase rotation in the clock-data-recovery circuit, the first rotate up and rotate down signals provided from a phase rotator control of a clock-data-recovery circuit to a reference clock of a serial receiver; and   combinatorial logic that adapts the phase adjusts to create future adjusts based on previous adjusts, including generating the future adjusts based on the accumulated phase adjust data and the previous adjusts, wherein the future adjusts include second rotate up and rotate down signals improving a rate of compensation for the frequency offsets by the phase adjusts, and wherein the first rotate up and rotate down signals and the second rotate up and rotate down signals are logically ORed to provide the phase adjusts to the reference clock.   
   
   
       10 . The circuit of  claim 9  wherein the combinatorial logic generates the second rotate up signal based on an overflow in the adder. 
   
   
       11 . The circuit of  claim 9  wherein the combinatorial logic generates the second rotate down signal based on an underflow in the adder. 
   
   
       12 . The circuit of  claim 9  wherein the combinatorial logic generates the second rotate up and rotate down signals through detection of overflow and underflow in the adder. 
   
   
       13 . The circuit of  claim 9  wherein the adder accumulates a chosen number of most significant bits of the up-down counter.