Integrated circuit device and method

Abstract

An integrated circuit device includes a semiconductor chip with a metallization layer on the chip. A gas-phase deposited insulation layer is disposed on the metallization layer.

1 . An integrated circuit device, comprising:
 a semiconductor chip;   a metallization layer on the chip; and   a gas-phase deposited insulation layer disposed on the metallization layer.   
   
   
       2 . The integrated circuit device of  claim 1 , wherein the gas-phase deposited insulation layer is thinner than 20 μm. 
   
   
       3 . The integrated circuit device of  claim 1 , wherein the metallization layer has a thickness of more than 10 nm. 
   
   
       4 . The integrated circuit device of  claim 1 , wherein the metallization layer includes at least one of copper, gold and palladium. 
   
   
       5 . The integrated circuit device of  claim 1 , wherein the metallization layer includes a plurality of layers. 
   
   
       6 . The integrated circuit device of  claim 1 , further comprising an encapsulation material deposited over the gas-phase deposited insulation layer. 
   
   
       7 . The integrated circuit device of  claim 1 , wherein the gas-phase deposited layer includes an inorganic material. 
   
   
       8 . The integrated circuit device of  claim 1 , wherein the gas-phase deposited layer includes a ceramic material. 
   
   
       9 . The integrated circuit device of  claim 1 , wherein the gas-phase deposited layer includes at least one of silica, silica nitride, CVD diamond, titanium dioxide, zirconium oxide, diamond-like carbon (DLC), amorphous carbon, parylene, and/or teflon. 
   
   
       10 . The integrated circuit device of  claim 1 , wherein the gas-phase deposited layer includes an organic polymeric material, and further comprising an adhesion-promoting layer over the insulation layer. 
   
   
       11 . The integrated circuit device of  claim 1 , wherein the metallization layer includes a trench including sidewalls and a floor, and wherein the gas-phase deposited insulation layer covers the sidewalls and the floor of the trench. 
   
   
       12 . A method for producing an integrated circuit device, comprising:
 providing a semiconductor chip;   applying a metallization layer to the semiconductor chip;   applying an insulation layer over the metallization layer by a gas-phase deposition.   
   
   
       13 . The method of  claim 12 , wherein applying the insulation layer includes depositing an inorganic precursor. 
   
   
       14 . The method of  claim 12 , further comprising structuring the insulation layer. 
   
   
       15 . The method of  claim 14 , wherein structuring the insulation layer includes depositing a mask layer. 
   
   
       16 . The method of  claim 14 , wherein structuring the insulation layer includes a photolithographic process. 
   
   
       17 . The method of  claim 14 , wherein structuring the insulation layer includes laser ablation. 
   
   
       18 . The method of  claim 12 , further comprising encapsulating the integrated circuit device. 
   
   
       19 . The method of  claim 12 , wherein the gas-phase deposition includes a chemical vapor deposition (CVD) process. 
   
   
       20 . The method of  claim 12 , wherein the gas-phase deposition includes a plasma enhanced chemical vapor deposition (PE-CVD) process. 
   
   
       21 . The method of  claim 12 , further comprising applying an adhesion promoting layer over the insulation layer. 
   
   
       22 . The method of  claim 21 , wherein applying the adhesion promoting layer includes a gas phase deposition of silane. 
   
   
       23 . An integrated circuit device, comprising:
 a semiconductor chip;   a metallization layer on the chip; and   means disposed on the metallization layer for insulating the metallization layer.