Protocol aware digital channel apparatus

Abstract

In one embodiment, provided is a protocol specific circuit for simulating a functional operational environment into which a device-under-test is placed for functional testing. The protocol specific circuit includes a protocol aware circuit constructed to receive a non-deterministic signal communicated by a device-under-test and to control a transfer of the test stimulus signal to the device-under-test in response to the a non-deterministic signal.

1 . A protocol specific circuit for simulating a functional operational environment into which a device-under-test is placed for functional testing, the protocol specific circuit comprising a protocol aware circuit constructed to receive at least one non-deterministic signal communicated by a device-under-test and to control a transfer of at least one test stimulus signal to the device-under-test in response to the at least one non-deterministic signal. 
     
     
         2 . The protocol specific circuit of  claim 1 , wherein the protocol aware circuit is constructed to control the transfer of the test stimulus signal by selecting a test stimulus signal response based on the non-deterministic signal from the device-under-test and initiating transmission of the selected at least one test stimulus signal. 
     
     
         3 . The protocol specific circuit of  claim 1 , wherein the protocol specific circuit is constructed to receive the at least one non-deterministic signal communicated by a protocol specific device-under-test via pin electronics and to control transfer of the at least one test stimulus signal from a test signal generator to the device-under-test. 
     
     
         4 . The protocol specific circuit of  claim 3 , wherein the protocol specific circuit is constructed to store the at least one test stimulus signal from the test signal generator in a stimulus signal storage device. 
     
     
         5 . The protocol specific circuit of  claim 4 , wherein the stimulus signal storage device comprises at least one of: a) FIFO memory; or b) random access memory. 
     
     
         6 . The protocol specific circuit of  claim 1 , wherein the protocol specific circuit is constructed to store the at least one non-deterministic signal in a response signal storage device. 
     
     
         7 . The protocol specific circuit of  claim 6 , wherein the response signal storage device comprises at least one of: a) FIFO memory; or b) random access memory. 
     
     
         8 . The protocol specific circuit of  claim 6 , wherein the protocol specific circuit is constructed to extract the at least one non-deterministic signal from the response signal storage device for comparison by a failure processor with an expected response signal, and determine an operational condition of the device-under-test. 
     
     
         9 . The protocol specific circuit of  claim 1 , wherein the protocol specific circuit is constructed for mounting in automated test equipment to allow the automatic test equipment to simulate a functional operational environment into which the device-under-test is placed for functional testing and the protocol aware circuit interprets the at least one non-deterministic signal to determine a synchronization time and a latency time for transmission of the at least one test stimulus signal. 
     
     
         10 . A protocol specific circuit comprising a configurable protocol aware circuit capable of being preconfigured to communicate at least one test stimulus signal between a test signal generator and a specific device-under-test via pin electronics in response to a non-deterministic signal from the device-under-test. 
     
     
         11 . The protocol specific circuit of  claim 10 , wherein the protocol specific circuit is preconfigured to respond to a specific device-under-test in response to the non-deterministic signal comprising an asynchronously occurring signal from the device-under-test. 
     
     
         12 . The protocol specific circuit of  claim 10 , wherein the protocol specific circuit comprises a protocol decoder. 
     
     
         13 . The protocol specific circuit of  claim 10 , wherein the protocol specific circuit is programmable. 
     
     
         14 . The protocol specific circuit of  claim 13 , wherein the protocol specific circuit comprises a field programmable gate array. 
     
     
         15 . The protocol specific circuit of  claim 14 , wherein the field programmable gate array comprises the protocol aware circuit and a memory device, the protocol aware circuit being coupled to the memory device. 
     
     
         16 . The protocol specific circuit of  claim 15 , wherein the memory device comprises at least one of: a) FIFO memory; or b) random access memory. 
     
     
         17 . The protocol specific circuit of  claim 10 , wherein the protocol specific circuit comprises a memory buffer configured to store the at least one test stimulus signal generated by the test signal generator and to provide the stored test stimulus signal via the pin electronics, to the device-under-test in response to a non-deterministic signal from the device-under-test. 
     
     
         18 . The protocol specific circuit of  claim 17 , wherein the memory buffer comprises at least one of: a) FIFO memory; or b) random access memory. 
     
     
         19 . The protocol specific circuit of  claim 10 , wherein the protocol specific circuit further comprises a pass-through circuit coupled in parallel with the protocol aware for receiving deterministic signals from the device-under-test. 
     
     
         20 . Automated test equipment comprising a protocol aware channel for testing a device-under-test, the protocol aware channel comprising a protocol specific circuit coupled between a test signal generator and a pin electronics circuit, the protocol specific circuit being constructed to be capable of being preconfigured to respond to the protocol specific device-under-test in response to a non-deterministic signal from the device-under-test. 
     
     
         21 . The automated tester of  claim 20 , wherein the protocol specific circuit comprises a protocol decoder. 
     
     
         22 . The automated tester of  claim 20 , wherein the protocol specific circuit comprises a field programmable gate array. 
     
     
         23 . The automated tester of  claim 22 , wherein the field programmable gate array comprises a protocol aware circuit and a memory device, the protocol aware circuit being coupled to the memory device. 
     
     
         24 . The automated tester of  claim 20 , wherein the protocol specific circuit comprises a memory buffer configured to store the at least one test stimulus signal generated by the test signal generator and to provide the stored test stimulus signal via the pin electronics, to the device-under-test in response to a non-deterministic signal from the device-under-test. 
     
     
         25 . The automated tester of  claim 20 , wherein the protocol specific circuit further comprises a pass-through circuit coupled in parallel with a protocol aware circuit for receiving deterministic signals from the device-under-test.