Integrated circuit with dma module for loading portions of code to a code memory for execution by a host processor that controls a video decoder

Abstract

A system, method, and apparatus for dynamically booting processor code memory with a wait instruction is presented herein. A wait instruction precedes the transfer of a new code portion to the code memory. The wait instruction causes the processor to temporarily cease using the code memory. When the processor ceases using the code memory, the processor signals a direct memory access (DMA) module to transfer a new code portion to the code memory. The DMA module transfers the new code portion to the code memory and transmits a signal to the processor when the transfer is completed. The signal causes the processor to resume. When the processor resumes, the processor begins executing the instructions at the next code address.

1 . A method for executing a program, said method comprising:
 executing a portion of the program; and   executing an instruction responsive to executing the portion of the program, wherein execution of the instruction causes cessation of program execution until another portion of the program is available for execution.   
   
   
       2 . The method of  claim 1 , further comprising:
 executing the another portion of the program.   
   
   
       3 . The method of  claim 2 , wherein executing the another portion of the program further comprises:
 receiving an indication that the another portion of the program is available for execution; and   executing at least one instruction from the another portion of the program responsive to receiving the indication.   
   
   
       4 . A method for executing instructions, said method comprising:
 fetching a first instruction;   decoding the first instruction; and   waiting until a portion of a program is available for processing before fetching a second instruction, wherein the first instruction is a wait instruction.   
   
   
       5 . The method of  claim 4 , further comprising:
 transmitting a first signal, wherein the first instruction is a wait instruction.   
   
   
       6 . The method of  claim 5 , further comprising:
 transferring the portion of the program responsive to transmitting the first signal.   
   
   
       7 . The method of  claim 4 , further comprising:
 receiving a signal indicating the portion of the program is available for execution.   
   
   
       8 . A circuit for executing a program, said circuit comprising:
 a code memory for storing a portion of the program and a particular instruction;   a processor for executing the portion of the program and the particular instruction; and   wherein execution of the instruction by the processor causes cessation of program execution until another portion of the program is stored in the code memory.   
   
   
       9 . The circuit of  claim 8 , wherein the processor executes the another portion of the program responsive to storage of the another portion of the program in code memory. 
   
   
       10 . The circuit of  claim 8 , further comprising:
 a direct memory access module for loading the code memory with the another portion of the program.   
   
   
       11 . The circuit of  claim 10 , wherein the direct memory access module transmits an indication that the another portion of the program is stored in the code memory and wherein the processor executes at least one instruction from the another portion of the program responsive to receiving the indication. 
   
   
       12 . The circuit of  claim 9 , wherein the processor further comprises:
 a fetch stage for fetching the particular instruction from the code memory;   a decode stage for decoding the particular instruction;   an execution stage for executing the particular instruction; and   wherein the fetch stage waits until the another particular portion of the program is stored in the code memory before fetching a second instruction, responsive to the execution stage executing the particular instruction.   
   
   
       13 . A processor for executing instructions, said processor comprising:
 a fetch stage connected to a code memory;   a decode stage connected to the fetch stage;   an execution stage connected to the decode stage; and   a link connecting the execution stage to the fetch stage, wherein the execution stage transmits a signal over the link causing the fetch stage to cease fetching instructions from the code memory.