Fully integrated compact cross-coupled low noise amplifier

Abstract

Fully integrated compact cross-coupled low noise amplifier. A circuitry implementation that includes two pairs of metal oxide semiconductor field-effect transistors (MOSFETs) (either N-type of P-type) operates as an LNA, which can be used within any of a wide variety of communication devices. A majority of the elements are integrated within the design and need not be implemented off-chip, and this can provide for a reduction in area required by the circuitry. A differential 100Ω input impedance is provided by this design. A higher than typical power supply voltage can be employed (if desired) to accommodate one possible implementation that includes two parallel implemented resistors to ground.

1 . An LNA (Low Noise Amplifier) circuitry, the circuitry comprising:
 a differential input that corresponds to a first node of a first capacitor and a first node of a second capacitor;   first and second N-MOSFETs;   third and fourth n-channel metal oxide semiconductor field-effect transistors (N-MOSFETs), wherein:
 each of a gate of the third N-MOSFET and a gate of the fourth N-MOSFET is connected to a bias voltage; 
 a drain of the first N-MOSFET couples to a source of the third N-MOSFET; and 
 a drain of the second N-MOSFET couples to a source of the fourth N-MOSFET; 
   a third capacitor having a first node coupled to a second node of the first capacitor and having a second node coupled to a gate of the first N-MOSFET;   a fourth capacitor having a first node coupled to a second node of the second capacitor and having a second node coupled to a gate of the second N-MOSFET a fifth N-MOSFET having a drain that is coupled to a source of the first N-MOSFET and having a source that is coupled to a ground voltage; and   a sixth N-MOSFET having a drain that is coupled to a source of the second N-MOSFET and having a source that is coupled to the ground voltage; and wherein:   each of the fifth N-MOSFET and the sixth N-MOSFET is implemented in a non-tri-well configuration such that each of a source of the fifth N-MOSFET and a source of the sixth N-MOSFET is not connected to a substrate of the circuitry.   
     
     
         2 . The circuitry of  claim 1 , wherein:
 each of the first N-MOSFET and the second N-MOSFET is implemented in a tri-well configuration such that each of a source of the first N-MOSFET and a source of the second N-MOSFET is connected to the substrate of the circuitry; and   each of the third N-MOSFET and the fourth N-MOSFET is implemented in a tri-well configuration such that each of a source of the third N-MOSFET and a source of the fourth N-MOSFET is connected to the substrate of the circuitry.   
     
     
         3 . The circuitry of  claim 1 , further comprising:
 a first resistor coupled between the second node of the third capacitor and at least one additional bias voltage; and   a second resistor coupled between the second node of the fourth capacitor and the at least one additional bias voltage.   
     
     
         4 . The circuitry of  claim 1 , further comprising:
 a first resistor coupled between a source of the first N-MOSFET and a ground voltage; and   a second resistor coupled between a source of the second N-MOSFET and the ground voltage.   
     
     
         5 . The circuitry of  claim 1 , wherein:
 each of a gate of the fifth N-MOSFET and a gate of the sixth N-MOSFET is coupled to at least one additional bias voltage.   
     
     
         6 . The circuitry of  claim 1 , further comprising:
 a first inductor coupled between a drain of the third N-MOSFET and a power supply voltage; and   a second inductor coupled between a drain of the fourth N-MOSFET and the power supply voltage.   
     
     
         7 . The circuitry of  claim 1 , wherein:
 an inductor is coupled between the first node of the first capacitor and the first node of the second capacitor.   
     
     
         8 . The circuitry of  claim 1 , wherein:
 the circuitry is implemented within a radio of a communication device.   
     
     
         9 . The circuitry of  claim 1 , wherein:
 the circuitry is implemented within a wireless communication device.   
     
     
         10 . The circuitry of  claim 1 , wherein:
 the circuitry is an integrated circuit.   
     
     
         11 . An LNA (Low Noise Amplifier) circuitry, the circuitry comprising:
 a differential input that corresponds to a first node of a first capacitor and a first node of a second capacitor;   first and second N-MOSFETs;   third and fourth n-channel metal oxide semiconductor field-effect transistors (N-MOSFETs), wherein:
 each of a gate of the third N-MOSFET and a gate of the fourth N-MOSFET is connected to a first bias voltage; 
 a drain of the first N-MOSFET couples to a source of the third N-MOSFET; and 
 a drain of the second N-MOSFET couples to a source of the fourth N-MOSFET; 
   a third capacitor having a first node coupled to a second node of the first capacitor and having a second node coupled to a gate of the first N-MOSFET;   a fourth capacitor having a first node coupled to a second node of the second capacitor and having a second node coupled to a gate of the second N-MOSFET;   a first inductor coupled between a drain of the third N-MOSFET and a power supply voltage;   a second inductor coupled between a drain of the fourth N-MOSFET and the power supply voltage;   a first resistor coupled between the second node of the third capacitor and a second bias voltage;   a second resistor coupled between the second node of the fourth capacitor and the second bias voltage;   a third resistor coupled between a source of the first N-MOSFET and a ground voltage; and   a fourth resistor coupled between a source of the second N-MOSFET and the ground voltage.   
     
     
         12 . The circuitry of  claim 11 , wherein:
 a third inductor is coupled between the first node of the first capacitor and the first node of the second capacitor.   
     
     
         13 . The circuitry of  claim 11 , wherein:
 the circuitry is implemented within a wireless communication device.   
     
     
         14 . The circuitry of  claim 11 , wherein:
 the circuitry is implemented within a radio of a wireless communication device.   
     
     
         15 . The circuitry of  claim 11 , wherein:
 the circuitry is an integrated circuit.   
     
     
         16 . An LNA (Low Noise Amplifier) circuitry, the circuitry comprising:
 a differential input that corresponds to a first node of a first capacitor and a first node of a second capacitor;   first and second N-MOSFETs;   third and fourth n-channel metal oxide semiconductor field-effect transistors (N-MOSFETs), wherein:
 each of a gate of the third N-MOSFET and a gate of the fourth N-MOSFET is connected to a first bias voltage; 
 a drain of the first N-MOSFET couples to a source of the third N-MOSFET; and 
 a drain of the second N-MOSFET couples to a source of the fourth N-MOSFET; 
   a third capacitor having a first node coupled to a second node of the first capacitor and having a second node coupled to a gate of the first N-MOSFET;   a fourth capacitor having a first node coupled to a second node of the second capacitor and having a second node coupled to a gate of the second N-MOSFET;   a first inductor coupled between a drain of the third N-MOSFET and a power supply voltage;   a second inductor coupled between a drain of the fourth N-MOSFET and the power supply voltage;   a first resistor coupled between the second node of the third capacitor and a second bias voltage;   a second resistor coupled between the second node of the fourth capacitor and the second bias voltage;   a fifth N-MOSFET having a drain that is coupled to a source of the first N-MOSFET and having a source that is coupled to a ground voltage; and   a sixth N-MOSFET having a drain that is coupled to a source of the second N-MOSFET and having a source that is coupled to the ground voltage; and wherein:   each of a gate of the fifth N-MOSFET and a gate of the sixth N-MOSFET is coupled to a third bias voltage.   
     
     
         17 . The circuitry of  claim 16 , wherein:
 a third inductor is coupled between the first node of the first capacitor and the first node of the second capacitor.   
     
     
         18 . The circuitry of  claim 16 , wherein:
 the circuitry is implemented within a wireless communication device.   
     
     
         19 . The circuitry of  claim 16 , wherein:
 the circuitry is implemented within a radio of a wireless communication device.   
     
     
         20 . The circuitry of  claim 16 , wherein:
 the circuitry is an integrated circuit.