Microcrystalline silicon deposition for thin film solar applications
Abstract
Embodiments of the invention as recited in the claims relate to thin film multi-junction solar cells and methods and apparatuses for forming the same. In one embodiment a method of forming a thin film multi-junction solar cell over a substrate is provided. The method comprises positioning a substrate in a reaction zone, providing a gas mixture to the reaction zone, wherein the gas mixture comprises a silicon containing compound and hydrogen gas, forming a first region of an intrinsic type microcrystalline silicon layer on the substrate at a first deposition rate, forming a second region of the intrinsic type microcrystalline silicon layer on the substrate at a second deposition rate higher than the first deposition rate, and forming a third region of the intrinsic type microcrystalline silicon layer on the substrate at a third deposition rate lower than the second deposition rate.
Claims
exact text as granted — not AI-modified1 - 8 . (canceled)
9 . A method of forming a thin film multi-junction solar cell over a substrate, comprising:
forming a first p-i-n junction, comprising:
forming a p-type amorphous silicon layer;
forming an intrinsic type amorphous silicon layer over the p-type amorphous silicon layer; and
forming a first n-type silicon layer over the intrinsic type amorphous silicon layer; and
forming a second p-i-n junction over the first p-i-n junction, comprising:
forming a p-type microcrystalline silicon layer;
forming an intrinsic type microcrystalline silicon layer over the p-type microcrystalline silicon layer, wherein forming the intrinsic type microcrystalline silicon layer comprises:
forming a first region of the intrinsic type microcrystalline silicon layer at a first deposition rate;
forming a second region of the intrinsic type microcrystalline silicon layer at a second deposition rate higher than the first deposition rate; and
forming a third region of the intrinsic type microcrystalline silicon layer at a third deposition rate lower than the second deposition rate; and
forming a second n-type silicon layer over the intrinsic type microcrystalline layer.
10 . The method of claim 9 , wherein forming an intrinsic type microcrystalline silicon layer further comprises forming a seed layer prior to forming a first region of the intrinsic type microcrystalline silicon layer.
11 . The method of claim 10 , further comprising forming an amorphous silicon barrier layer between the p-type microcrystalline silicon layer and the seed layer.
12 . The method of claim 9 , further comprising forming an amorphous silicon barrier layer between the p-type microcrystalline silicon layer and the intrinsic type microcrystalline silicon layer.
13 . The method of claim 9 , wherein the first p-i-n junction is formed over a tin oxide transparent conducting oxide layer.
14 . The method of claim 9 , wherein the first region of the intrinsic type microcrystalline silicon layer is formed to a thickness between about 10 Å and about 500 Å, wherein the second region of the intrinsic type microcrystalline silicon layer is formed to a thickness between about 10,000 Å and about 30,000 Å, and wherein the third region of the intrinsic type microcrystalline silicon layer is between about 10 Å and about 500 Å.
15 . The method of claim 9 , wherein the first deposition rate is between about 100 Å/minute and about 350 Å/minute, wherein the second deposition rate is between about 400Å/minute and about 1500Å/minute, and wherein the third deposition rate is between about 100 Å/minute and about 350 Å/minute.
16 . The method of claim 9 , wherein the p-type amorphous silicon layer of the first p-i-n junction is formed to a thickness between about 60Å and about 300Å; wherein the intrinsic type amorphous silicon layer of the first p-i-n junction is formed to a thickness between about 1,500 Å and about 3,500 Å; and wherein the n-type silicon layer of the first p-i-n junction is formed to a thickness between about 100 Å and about 400 Å.
17 . The method of claim 9 , wherein the p-type microcrystalline silicon layer of the second p-i-n junction is formed to a thickness between about 100 Å and about 400 Å; wherein the intrinsic type microcrystalline silicon layer of the second p-i-n junction is formed to a thickness between about 10,000 Å and about 30,000 Å; and wherein the second n-type silicon layer is formed to a thickness between about 100 Å and about 500 Å.
18 . The method of claim of claim 11 , wherein the amorphous silicon barrier layer is formed to a thickness between about 20 Å and about 100 Å.
19 . The method of claim 9 , wherein the first p-i-n junction is formed in a first process system comprising a first process chamber and a second process chamber.
20 . The method of claim 9 , wherein the p-type amorphous silicon layer of the first p-i-n junction is formed in the first process chamber of the first process system and wherein the intrinsic type amorphous silicon layer and the n-type silicon layer are formed in the second process chamber of the first process system.
21 . The method of claim 12 , wherein the second p-i-n junction is formed in a second process system comprising a first process chamber and a second process chamber.
22 . The method of claim 14 , wherein the p-type microcrystalline silicon layer of the second p-i-n junction is formed in the first process chamber of the second process system and wherein the intrinsic type microcrystalline silicon layer and the n-type microcrystalline or amorphous silicon layer of the second p-i-n junction is formed in the second chamber of the second process system.
23 . The method of claim 9 , wherein the first n-type silicon layer and the second n-type silicon layer are an n-type amorphous silicon layer or an n-type microcrystalline silicon layer.
24 . The method of claim 10 , wherein the seed layer is formed to a thickness between about 20 Å and about 500 Å.Join the waitlist — get patent alerts
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