Process of multiple exposures with spin castable film

Abstract

Methods of multiple exposure in the fields of deep ultraviolet photolithography, next generation lithography, and semiconductor fabrication comprise a spin-castable methodology for enabling multiple patterning by completing a standard lithography process for the first exposure, followed by spin casting an etch selective overcoat layer, applying a second photoresist, and subsequent lithography. Utilizing the etch selectivity of each layer, provides a cost-effective, high resolution patterning technique. The invention comprises a number of double or multiple patterning techniques, some aimed at achieving resolution benefits, as well as others that achieve cost savings, or both resolution and cost savings. These techniques include, but are not limited to, pitch splitting techniques, pattern decomposition techniques, and dual damascene structures.

1 . A process of enhancing photolithography resolution for patterning a semiconductor device comprising:
 a. exposing a first layer in a semiconductor device to obtain a first structure comprising a first set of patterned features in a first photoresist layer;   b. applying an etch selective overcoat material over said first structure;   c. exposing a second layer in said semiconductor device to obtain a second structure comprising a second set of patterned features in a second photoresist layer;   d. transferring, both said second set of patterned features and said first set of patterned features into an underlying substrate layer on said semiconductor device, wherein said first set of patterned features and said second set of patterned features are combined into a composite set of patterned features transferable into said underlying substrate layer.   
     
     
         2 . The process of  claim 1 , wherein said etch selective overcoat material is applied over said set first set of patterned features in said first photoresist layer by means of a spin on process. 
     
     
         3 . The process of  claim 1 , wherein
 a. said etch selective overcoat material comprises an inorganic intermediate layer formed over said first structure comprising a first set of patterned features in a photoresist layer;   b producing said first set of patterned features by a process comprising patterning an organic photoresist material operatively associated with said semiconductor device; and   c. producing said second structure by a process comprising patterning an organic photoresist material operatively associated with said semiconductor device.   
     
     
         4 . The process of  claim 3 , wherein said inorganic intermediate layer comprises a silicon containing intermediate layer 
     
     
         5 . The process of  claim 1  wherein:
 a. said etch selective overcoat material comprises an organic layer formed over said first structure;   b. forming said first set of patterned features by patterning a silicon containing photoresist operatively associated with said semiconductor device; and   c. forming said second set of patterned features by patterning a silicon containing photoresist operatively associated with said semiconductor device.   
     
     
         6 . The process of  claim 1 , comprising:
 a. forming said etch selective overcoat material from a first organic layer over said first structure in combination with a first inorganic layer on top of said first organic layer;   b. forming said first set of patterned features by patterning a silicon containing photoresist; and   c. forming said second set of patterned features by patterning an organic photoresist   
     
     
         7 . The process of  claim 6 , wherein said inorganic layer is a silicon containing intermediate layer. 
     
     
         8 . The process of  claim 1 , comprising applying a bottom antireflective coating under said first structure. 
     
     
         9 . A process of enhancing photolithography resolution for patterning a semiconductor device comprising:
 a. providing a semiconductor device having obtain a first structure comprising a first set of patterned features in a first photoresist layer;   b. applying an etch selective overcoat material over said first structure and exposing said first structure;   c. providing a second layer in said semiconductor device to obtain a second structure comprising a second set of patterned features in a second photoresist layer and exposing said second structure;   c. transferring both said second set of patterned features and said first set of patterned features into an underlying substrate layer on said semiconductor device, wherein said first set of patterned features and said second set of patterned features are combined into a composite set of patterned features transferable into said substrate and further comprising;   d. forming an immersion top coating on top of said first structure and said second structure before said exposure   
     
     
         10 . The process of  claim 1 , wherein said first exposure and said second exposure are implemented through a mask comprising a dark field mask. 
     
     
         11 . The process of  claim 1 , wherein said first exposure and said second exposure are implemented through a mask comprising a bright field mask. 
     
     
         12 . The process of  claim 1 , wherein said first exposure is implemented through a mask comprising a dark field mask, and said second exposure is implemented through a mask comprising a bright field mask. 
     
     
         13 . The process of  claim 1 , wherein said first exposure is implemented through a mask comprising a bright field mask, and said second exposure is implemented through a mask comprising a dark field mask. 
     
     
         14 . The process of  claim 1 , wherein said etch selective overcoat comprises an overcoat having antireflective properties. 
     
     
         15 . The process of  claim 1 , wherein said etch selective overcoat comprises an organic coating and further comprising cross linking said organic coating during post apply processing. 
     
     
         16 . A via structure generated by the process of  claim 1 . 
     
     
         17 . A dual damascene structure generated by the process of  claim 1 . 
     
     
         18 . A CMOS device with a gate patterned by the process of  claim 1 . 
     
     
         19 . An interconnect structure selected from interconnected semiconductor devices and interconnected optical communication devices where said interconnect structure is patterned by the process of  claim 1 .