Semiconductor memory device

Abstract

Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.

1 - 20 . (canceled) 
   
   
       21 . A semiconductor memory device, comprising:
 a plurality of memory cells arranged in row and columns, each of said memory cells including a capacitor including a cell plate electrode and a storage electrode arranged facing to said cell plate electrode, for accumulating electric charges corresponding to storage data, the cell plate electrode receiving a predetermined voltage;   a plurality of word lines arranged corresponding to the rows of memory cells and each connecting to the memory cells in a corresponding row, said word lines being formed in a same interconnection layer as the cell plate electrodes;   a plurality of bit lines arranged corresponding to the columns of memory cells and each connecting to the memory cells on a corresponding column, the bit lines being arranged in pairs;   row selecting circuitry for selecting an addressed word line out of the word lines in accordance with an address signal, the memory cells being arranged such that data in selected memory cells on an addressed row are simultaneously read out onto bit lines in a pair by a selected word line, said row selecting circuitry driving said addressed word line into a voltage level equal to a voltage of said cell plate electrode; and   a bit line voltage setting circuit for setting the respective bit lines to a voltage level equal to the voltage of the addressed, selected word line in a standby.   
   
   
       22 . The semiconductor memory device according to  claim 21 , wherein the voltage of the cell plate electrode and the voltage of the bit lines set in the standby are a power supply voltage level. 
   
   
       23 . The semiconductor memory device according to  claim 22 , wherein a region for constituting the storage electrode comprise an impurity region of a first impurity concentration, and a region electrically connected to said impurity region and arranged facing to said cell plate electrode, and said first impurity concentration is lower than an impurity concentration of a corresponding impurity region of a peripheral transistor included in a peripheral circuit.