Semiconductor device including detector circuit capable of performing high-speed operation

Abstract

A detector circuit and a negative voltage generating circuit capable of performing a high-speed operation are provided. A negative voltage generating circuit includes a charge pump circuit, a first voltage divider circuit that makes a voltage division between an output of the charge pump circuit and a power supply to output a detect potential, a reference voltage generating circuit that generates a reference potential, and a comparator circuit that compares the detect potential and the reference potential. The charge pump circuit is driven by an output signal of the comparator circuit and generates the negative voltage. In the first voltage divider circuit, NMOS transistors make the voltage division between the negative voltage and the power supply to obtain the detect potential.

1 - 11 . (canceled) 
   
   
       12 . A semiconductor device comprising a reference potential generating circuit that generates a reference potential,
 wherein said reference potential generating circuit includes a first divider circuit generating said reference potential by obtaining an intermediate reference potential from a voltage division between a first voltage potential and a second voltage potential; and   wherein said reference potential generating circuit further includes an adjustment circuit decreasing said reference potential by a predetermined adjustment value to obtain said reference potential.   
   
   
       13 . A semiconductor device comprising a detector circuit that detects a level of a first voltage, and a reference potential generating circuit that generates a reference potential,
 wherein said detector circuit includes a first divider circuit including a plurality of MOS transistors connected in series between a potential of said first voltage and a potential of second voltage, said plurality of MOS transistors being configured to cause a voltage division between said first voltage potential and said second voltage potential, and said first driver circuit being configured to output a detect potential generated by the voltage division between said first voltage potential and said second voltage potential;   wherein said reference potential generating circuit includes a second divider circuit generating said reference potential by obtaining an intermediate reference potential from a voltage division between said second voltage potential and a third voltage potential;   wherein said reference potential generating circuit further includes an adjustment circuit decreasing said reference potential by a predetermined adjustment value to obtain said reference potential;   wherein said detector circuit further includes first and second level shift circuits that respectively shift said detect potential and said reference potential to predetermined potential levels;   wherein said detector circuit further includes a comparator circuit compares said level-shifted detect potential and said level-shifted reference potential respectively outputted by said first and second level shift circuits; and   wherein said semiconductor device further comprises a charge pump circuit being driven by an output signal from said comparator circuit to generate said first voltage in accordance with said reference potential.   
   
   
       14 . The semiconductor device according to claim  2 , further comprising:
 a DRAM (Dynamic Random Access Memory) cell; and   a word line driver that drives a word line of said DRAM cell,   said word line driver comprising an NMOS transistor having its drain connected to said word line and its source supplied with said first voltage.