US2009102061A1PendingUtilityA1

Self-Aligned Wafer Level Integration System

Assignee: PURDUE RESEARCH FOUNDATIONPriority: Jan 31, 2005Filed: Nov 26, 2008Published: Apr 23, 2009
Est. expiryJan 31, 2025(expired)· nominal 20-yr term from priority
H10W 72/9413H10W 90/00H10W 70/093H10W 70/09H10W 70/60H10W 90/10H10P 72/7424H10W 74/019H10W 70/614H10P 72/74
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Claims

Abstract

A polymer-based, self-aligned wafer-level heterogeneous integration system, SAWLIT, for integrating semiconductor integrated circuit (IC) chips to a substrate is presented. The system includes a method including preparing a substrate, flipping the substrate onto a polymer-based flat surface and securing the substrate to the flat surface, mounting semiconductor chips into the prepared substrate, integrating the chips to the substrate with another polymer-based material, and removing the resulting multi-chip module from the flat surface. The chips may then be connected with each other and regions off the multi-chip module with metal interconnect processing technology. A multi-chip module prepared by the polymer-based, self-aligned heterogeneous integration system including semiconductor chips mounted in a prepared substrate. The chips may be connected to the substrate by a polymer-based integrating material.

Claims

exact text as granted — not AI-modified
1 - 14 . (canceled) 
     
     
         15 . A semiconductor multi-chip module comprising a plurality of semiconductor chips, a substrate into which the plurality of semiconductor chips are mounted, and a polymer-based integrating material connecting the plurality of semiconductor chips to the substrate. 
     
     
         16 . A semiconductor multi-chip module as in  claim 15  further comprising a plurality of metal interconnect lines connecting the plurality of semiconductor chips with each other. 
     
     
         17 . A semiconductor multi-chip module as in  claim 15  further comprising a plurality of metal interconnect lines connecting the plurality of semiconductor chips to regions off the multi-chip module. 
     
     
         18 . A semiconductor multi-chip module as in  claim 16 , where the plurality of metal interconnect lines are composed of at least one of a metal or a metal alloy selected from the group comprising: Au, Cu, and Al. 
     
     
         19 . A semiconductor multi-chip module as in  claim 15  where the substrate is composed of any of the following: Si, Quartz, GaAs, a ceramic substrate, or LCP. 
     
     
         20 . The semiconductor multi-chip module as in  claim 15  where the polymer-based integrating material is a polydimethylsiloxane (PDMS), ultraviolet (UV) cure epoxy resin or adhesive, an electronic grade encapsulant, a die attach adhesive, an epoxy, deposited amorphous Si, or deposited or electroplated Au, Cu, or Al or combination thereof. 
     
     
         21 . (canceled)

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