Bipolar transistors with resistors

Abstract

Bipolar transistors in complimentary MOS (CMOS) integrated circuits (ICs) are often fabricated as parasitic components, in which emitters of bipolar transistors are implanted in the same processes as CMOS sources/drains, to avoid manufacturing costs associated with dedicated implants for bipolar emitters. Energies and doses of CMOS source/drain implants are typically selected to optimize CMOS transistor performance, resulting in less than optimum values of bipolar parameters such as gain. CMOS ICs often include implanted resistors of a same type as the emitters of the bipolar transistors in the same ICs. This invention discloses bipolar transistors with emitters implanted by CMOS source/drain implants and resistor implants to improve bipolar transistor parameters, and a method for fabricating same.

1 . An integrated circuit, comprising
 provided a substrate;   an MOS transistor, comprising source and drain regions which are ion implanted with a first dopant at an energy from 1 to 300 keV and a dose from 10 14  to 10 16  cm −2 ;   a resistor, comprising a body region which is ion implanted with a second dopant, of the same type polarity as the first dopant, at an energy from 1 to 300 keV and a dose from 10 14  to 10 16  cm −2 ; and   a bipolar transistor, comprising an emitter which is ion implanted with said first dopant simultaneously with said source and drain regions of said MOS transistor and is ion implanted with said second dopant simultaneously with said body region of said resistor.   
   
   
       2 . The integrated circuit of  claim 1 , wherein said body region of said resistor is comprised of polycrystalline silicon. 
   
   
       3 . The integrated circuit of  claim 1 , wherein said body region of said resistor is comprised of an active region in said substrate. 
   
   
       4 . The integrated circuit of  claim 1 , wherein:
 said MOS transistor is a p-channel MOS transistor;   said first dopant is a p-type dopant;   said second dopant is a p-type dopant; and   said bipolar transistor is a vertical pnp bipolar transistor.   
   
   
       5 . The integrated circuit of  claim 1 , wherein:
 said MOS transistor is an n-channel MOS transistor;   said first dopant is an n-type dopant;   said second dopant is an n-type dopant; and   said bipolar transistor is a buried collector npn bipolar transistor.   
   
   
       6 . The integrated circuit of  claim 1 , wherein:
 said MOS transistor is an n-channel MOS transistor;   said first dopant is an n-type dopant;   said second dopant is an n-type dopant; and   said bipolar transistor is a lateral npn bipolar transistor.   
   
   
       7 . The integrated circuit of  claim 1 , wherein:
 said MOS transistor is a p-channel MOS transistor;   said first dopant is a p-type dopant;   said second dopant is a p-type dopant; and   said bipolar transistor is a lateral pnp bipolar transistor.   
   
   
       8 . A method of forming an integrated circuit, comprising the steps of:
 providing a substrate;   forming an MOS transistor, by a process comprising the steps of:
 defining source and drain regions; and 
 ion implanting a first dopant in said source and drain regions at an energy from 1 to 300 keV and a dose from 10 14  to 10 16  cm −2 ; 
   forming a resistor, by a process comprising the steps of:
 defining a body region; and 
 ion implanting a second dopant of the same type polarity as the first dopant in said body region at an energy from 1 to 300 keV and a dose from 10 14  to 10 16  cm −2 ; 
   forming a bipolar transistor, by a process comprising the steps of:
 defining an emitter region; 
 ion implanting said emitter region with said first dopant simultaneously with said source and drain regions of said MOS transistor; and 
 ion implanting said emitter region with said second dopant simultaneously with said body region of said resistor. 
   
   
   
       9 . The method of  claim 8 , wherein said process of forming a resistor further comprises the step of forming said body region of polycrystalline silicon. 
   
   
       10 . The method of  claim 8 , wherein said process of forming a resistor further comprises the step of forming said body region in an active region of said substrate. 
   
   
       11 . The method of  claim 8 , wherein:
 said MOS transistor is a p-channel MOS transistor;   said first dopant is a p-type dopant;   said second dopant is a p-type dopant; and   said bipolar transistor is a vertical pnp bipolar transistor.   
   
   
       12 . The method of  claim 8 , wherein:
 said MOS transistor is an n-channel MOS transistor;   said first dopant is an n-type dopant;   said second dopant is an n-type dopant; and   said bipolar transistor is a buried collector npn bipolar transistor.   
   
   
       13 . The method of  claim 8 , wherein:
 said MOS transistor is an n-channel MOS transistor;   said first dopant is an n-type dopant;   said second dopant is an n-type dopant; and   said bipolar transistor is a lateral npn bipolar transistor.   
   
   
       14 . The method of  claim 8 , wherein:
 said MOS transistor is a p-channel MOS transistor;   said first dopant is a p-type dopant;   said second dopant is a p-type dopant; and   said bipolar transistor is a lateral pnp bipolar transistor.   
   
   
       15 . A method of forming an integrated circuit, comprising the steps of:
 providing a substrate;   forming an MOS transistor, by a process comprising the steps of:
 defining source and drain regions; and 
 ion implanting a first dopant in said source and drain regions at an energy from 1 to 300 keV and a dose from 10 14  to 10 16  cm −2 ; 
   forming a resistor, by a process comprising the steps of:
 defining a body region; and 
 ion implanting a second dopant of the same type polarity as the first dopant in said body region at an energy from 1 to 300 keV and a dose from 10 14  to 10 16  cm −2 ; 
   forming a first bipolar transistor, by a process comprising the steps of:
 defining a first emitter region; 
 ion implanting said first emitter region with said first dopant simultaneously with said source and drain regions of said MOS transistors; and 
 ion implanting said first emitter region with said second dopant simultaneously with said body region of said resistor; 
   forming a second bipolar transistor, by a process comprising the steps of:
 defining a second emitter region; and 
 ion implanting said second emitter region with said second dopant simultaneously with said body region of said resistor. 
   
   
   
       16 . The method of  claim 15 , wherein said process of forming a resistor further comprises the step of forming said body region of polycrystalline silicon. 
   
   
       17 . The method of  claim 15 , wherein said process of forming a resistor further comprises the step of forming said body region in an active region of said substrate. 
   
   
       18 . The method of  claim 15 , wherein
 said MOS transistor is a p-channel MOS transistor;   said first dopant is a p-type dopant;   said second dopant is a p-type dopant;   said first bipolar transistor is a vertical pnp bipolar transistor; and   said second bipolar transistor is a vertical pnp bipolar transistor.   
   
   
       19 . The method of  claim 15 , wherein
 said MOS transistor is an n-channel MOS transistor;   said first dopant is an n-type dopant;   said second dopant is an n-type dopant; and   said first bipolar transistor is a buried collector npn bipolar transistor;   said second bipolar transistor is a buried collector npn bipolar transistor.   
   
   
       20 . The method of  claim 15 , wherein
 said MOS transistor is an n-channel MOS transistor;   said first dopant is an n-type dopant;   said second dopant is an n-type dopant; and   said first bipolar transistor is a lateral npn bipolar transistor;   said second bipolar transistor is a lateral npn bipolar transistor.