Method and Apparatus for Managing Power Consumption Relating to a Differential Serial Communication Link

Abstract

Briefly, a method, apparatus and system for managing power corresponding to a differential serial communication link that has a link width defined for example by one or more lanes wherein the lanes are adapted to communicate clock recovery information in a data stream, determines, during normal operating conditions, such as conditions other than power on, reset or link fault conditions, a desired link width for the serial communication link and then changes the link width accordingly.

1 . A method for managing power of a communication link, said communication link comprising one or more lanes, said method comprising:
 changing a number of active lanes of the communication link during normal operation, said changing comprising transitioning to a link recovery state and transitioning to a configuration state without transitioning to a detect state.   
   
   
       2 . The method of  claim 1  further comprising:
 determining during said normal operation, a desired link width.   
   
   
       3 . The method of  claim 2  wherein said changing to said number of active lanes approximates said desired link width. 
   
   
       4 . A method for managing power of a communication link, said communication link comprising one or more lanes, said method comprising:
 changing a number of active lanes of the communication link during normal operation, said changing comprising transitioning to a link recovery state, transitioning to a configuration state and increasing a link width of the communication link.   
   
   
       5 . The method of  claim 4  further comprising:
 determining during said normal operation, a desired link width.   
   
   
       6 . The method of  claim 5  wherein said changing to said number of active lanes approximates said desired link width. 
   
   
       7 . The method of  claim 1  wherein the communication link is a differential serial communication link having a link width comprised of one or more lanes adapted to communicate clock recovery information in a data stream. 
   
   
       8 . The method of  claim 7  wherein the communication link is compliant with a peripheral component interface specification. 
   
   
       9 . [northbridge side of the circuit] An integrated circuit comprising:
 a memory bridge circuit operative to couple with a communication link, comprising dynamic link width control logic operative to change a number of active lanes of the communication link during normal operation, said changing comprising transitioning to a link recovery state and transitioning to a configuration state without transitioning to a detect state.   
   
   
       10 . The integrated circuit of  claim 9  wherein the dynamic link width control logic is operative to determine during said normal operation, a desired link width. 
   
   
       11 . An integrated circuit comprising:
 dynamic link width control logic operative to change a number of active lanes of a communication link during normal operation, said changing comprising transitioning to a link recovery state and transitioning to a configuration state without transitioning to a detect state.   
   
   
       12 . The integrated circuit of  claim 11  wherein the dynamic link width control logic is operative to determine during said normal operation, a desired link width.