Semiconductor device manufacturing method and semiconductor device manufacturing apparatus

Abstract

A semiconductor device manufacturing method and a semiconductor device manufacturing apparatus which enable to detect an etching end-point with high accuracy are provided. In etching of a lower layer formed on a semiconductor wafer using a mask which comprises a plurality of patterns extending in a predetermined direction (line-and-space patterns) and contains at least one of a metal layer and an electrically-conductive metal compound layer, the surface of the semiconductor wafer is irradiated with inspection light, the etching is performed while monitoring the intensity of the polarized light component perpendicular to the predetermined extending direction of the line-and-space patterns and the etching is terminated at the time the intensity of the polarized light component reaches a reflected light intensity corresponding to a desired remaining thickness of the lower layer.

1 . A semiconductor device manufacturing method for etching a lower layer corresponding to between plural patterns constituting a mask layer on a semiconductor wafer including the lower layer and the plural patterns formed on the lower layer to extend in a predetermined direction and contain at least one of a metal and an electrically-conductive metal compound, comprising the steps of:
 irradiating the semiconductor wafer with inspection light; and   determining an end-point of the etching, on the basis of intensity of a polarized light component perpendicular to the predetermined direction contained in reflected light of the inspection light which is reflected from the semiconductor wafer.   
   
   
       2 . The semiconductor device manufacturing method as claimed in  claim 1 , wherein said mask layer contain tungsten (W). 
   
   
       3 . The semiconductor device manufacturing method as claimed in  claim 1 , wherein said lower layer contains polycrystalline silicon. 
   
   
       4 . The semiconductor device manufacturing method as claimed in  claim 2 , wherein said lower layer contains polycrystalline silicon. 
   
   
       5 - 20 . (canceled) 
   
   
       21 . The semiconductor device manufacturing method as claimed in  claim 1 , further comprising a step for etching the lower layer by plasma etching using a first etching gas and using the mask layer such that the lower layer remains with a predetermined thickness and etching away the lower layer with the predetermined thickness by plasma etching using a second etching gas different from the first etching gas and using the mask layer. 
   
   
       22 . The semiconductor device manufacturing method as claimed in  claim 21 , wherein said first etching gas contains fluoro carbon and said second etching gas does not contain fluoro carbon. 
   
   
       23 . The semiconductor device manufacturing method as claimed in  claim 21 , wherein said lower layer contains polycrystalline silicon layer contains an N-type portion and a P-type portion. 
   
   
       24 . The semiconductor device manufacturing method as claimed in  claim 1 , further comprising a step for forming a silicon oxide layer on said semiconductor wafer prior to forming the lower layer and the surface of said silicon oxide layer is exposed by etching away the lower layer.