US2009096950A1PendingUtilityA1

Thin film transistor panel

Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Jan 14, 2005Filed: Oct 10, 2008Published: Apr 16, 2009
Est. expiryJan 14, 2025(expired)· nominal 20-yr term from priority
G02F 1/1393G02F 1/133753G02F 1/134309G02F 1/133707
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Claims

Abstract

A thin film transistor panel is provided. The thin film transistor panel includes: a substrate; gate lines formed on the substrate; data lines insulated from the gate lines and intersecting the gate lines; thin film transistors which are connected to the gate lines and the data lines and have drain electrodes; capacitive coupling electrodes connected to the drain electrodes; and pixel electrodes which are formed in the pixels surrounded by the gate lines and the data lines and include first pixel electrodes connected to the drain electrodes and second pixel electrodes which are separated from the first pixel electrodes and overlap with the capacitive coupling electrodes, wherein the first and second pixel electrodes of different pixel electrodes have a left-right symmetrical structure.

Claims

exact text as granted — not AI-modified
1 . A thin film transistor panel comprising:
 a substrate;   gate lines formed on the substrate;   data lines insulated from the gate lines and intersecting the gate lines;   a plurality of thin film transistors connected to the gate lines and the data lines, the thin film transistors each having a drain electrode;   a plurality of capacitive coupling electrodes each capacitive coupling electrode being associated with and connected to the drain electrode of the associated thin film transistor; and   a plurality of pixel electrodes arranged in a matrix each of the pixel electrodes comprising a first sub-pixel electrode and a second sub-pixel electrode, and each of the pixel electrodes being associated with a pixel area defined by the gate lines and the data lines, wherein the first and second sub-pixel electrodes of each pixel are connected to the drain electrode of the associated thin film transistor, and the second sub-pixel electrode is spaced apart from the first sub-pixel electrode and further wherein the first and second sub-pixel electrodes overlap the capacitive coupling electrodes,   wherein the second sub-pixel electrodes have a truncated triangular shape and the truncated shorter end in ones of the second sub-pixel electrodes face in a different direction than the truncated shorter ends of other of the second sub-pixel electrodes.

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