US2009096073A1PendingUtilityA1

Semiconductor device and lead frame used for the same

Assignee: TOSHIBA KKPriority: Oct 16, 2007Filed: Oct 16, 2008Published: Apr 16, 2009
Est. expiryOct 16, 2027(~1.2 yrs left)· nominal 20-yr term from priority
Inventors:Yoshiaki Goto
H10W 90/756H10W 90/752H10W 90/736H10W 90/732H10W 90/24H10W 74/00H10W 72/07353H10W 72/5525H10W 72/5522H10W 72/931H10W 72/884H10W 72/334H10W 72/0198H10W 72/50H10W 70/479H10W 70/433H10W 70/429H10W 90/811H10W 70/466H10W 70/465H10W 70/421H10W 70/417H10W 70/415H10W 74/127
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Claims

Abstract

A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame.

Claims

exact text as granted — not AI-modified
1 . A semiconductor device, comprising:
 a circuit substrate provided with an element-mounting region, an outer lead portion having a plurality of outer leads, an inner lead portion having a plurality of inner leads which are at least partly routed in the element-mounting region, and an insulation resin filled into gaps between the inner leads located on at least part of the element-mounting region;   a first element group, mounted on the element-mounting region in a first surface of the circuit substrate, including at least one first semiconductor element having electrode pads;   a second element group, mounted on the element-mounting region in a second surface of the circuit substrate, including at least one second semiconductor element having electrode pads;   first metal wires electrically connecting the electrode pads of the first semiconductor element and the inner leads of the circuit substrate;   second metal wires electrically connecting the electrode pads of the second semiconductor element and the inner leads of the circuit substrate; and   a resin-sealed portion sealing the first and second element groups together with the first and second metal wires.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein the insulation resin is previously filled in the gaps before the resin-sealed portion is formed.   
     
     
         3 . The semiconductor device according to  claim 1 ,
 wherein an insulation resin sheet having the insulation resin coated on a support film is compression-bonded to the element-mounting region of the circuit substrate to fill the insulation resin into the gaps.   
     
     
         4 . The semiconductor device according to  claim 1 ,
 wherein the outer lead portion is provided with a first outer lead portion having first outer leads and a second outer lead portion having second outer leads arranged to oppose to the first outer leads with the element-mounting region between them, and the inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads,   wherein at least either the first or second inner leads are routed in the element-mounting region.   
     
     
         5 . The semiconductor device according to  claim 4 ,
 wherein the first inner leads are arranged on the side of the first outer lead portion, and the second inner leads are routed from the second outer lead portion toward the first outer lead portion via the element-mounting region.   
     
     
         6 . The semiconductor device according to  claim 5 ,
 wherein at least either the first or second semiconductor element has the electrode pads arranged along a outline side and is mounted on the element-mounting region to have the electrode pads located on the side of the first outer lead portion.   
     
     
         7 . The semiconductor device according to  claim 4 ,
 wherein the first outer lead portion is arranged along a first outline side of the element-mounting region, the second outer lead portion is arranged along a second outline side of the element-mounting region to oppose to the first outline side, the first inner leads are routed from the first outer lead portion toward a third outline side of the element-mounting region to cross at right angles to the first outline side, and the second inner leads are routed from the second outer lead portion toward the third outline side of the element-mounting region.   
     
     
         8 . The semiconductor device according to  claim 7 ,
 wherein at least either the first or second semiconductor element has the electrode pads arranged along a outline side and is mounted on the element-mounting region to have the electrode pads located near the third outline side of the element-mounting region.   
     
     
         9 . The semiconductor device according to  claim 1 ,
 wherein the outer lead portion is provided with a first outer lead portion having first outer leads and a second outer lead portion having second outer leads arranged to oppose the first outer leads with the element-mounting region between them, and the inner lead portion has first inner leads connected to the first outer leads, second inner leads connected to the second outer leads, and third inner leads electrically independent of the first and second outer leads,   wherein the first, second and third inner leads are at least partly routed in the element-mounting region.   
     
     
         10 . The semiconductor device according to  claim 1 ,
 wherein the first semiconductor element and the second semiconductor element have substantially the same shape.   
     
     
         11 . The semiconductor device according to  claim 10 ,
 wherein the insulation resin is filled into the gaps between the whole inner leads arranged on the element-mounting region.   
     
     
         12 . The semiconductor device according to  claim 1 ,
 wherein the first semiconductor element has an outer shape smaller than the second semiconductor element.   
     
     
         13 . The semiconductor device according to  claim 12 ,
 wherein the insulation resin is filled into the gaps between the inner leads located in a region where at least the first semiconductor element and the second semiconductor element are overlapped.   
     
     
         14 . A semiconductor device, comprising:
 a circuit substrate provided with an element-mounting region, an outer lead portion having a plurality of outer leads, an inner lead portion having a plurality of inner leads which are connected to the outer leads and at least partly routed in the element-mounting region, and an insulation resin filled into the gaps between the inner leads located on the element-mounting region;   a first element group, mounted on the element-mounting region in a first surface of the circuit substrate, including a plurality of first semiconductor elements having electrode pads;   a second element group, mounted on the element-mounting region in a second surface of the circuit substrate, including a plurality of second semiconductor elements having electrode pads;   first metal wires electrically connecting the electrode pads of the first semiconductor elements and the inner leads of the circuit substrate;   second metal wires electrically connecting the electrode pads of the second semiconductor elements and the inner leads of the circuit substrate; and   a resin-sealed portion sealing the first and second element groups together with the first and second metal wires.   
     
     
         15 . The semiconductor device according to  claim 14 ,
 wherein the insulation resin is previously filled into the gaps before the resin-sealed portion is formed.   
     
     
         16 . The semiconductor device according to  claim 14 ,
 wherein the outer lead portion is provided with a first outer lead portion having first outer leads and a second outer lead portion having second outer leads arranged to oppose to the first outer leads with the element-mounting region between them, and the inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads,   wherein at least either the first or second inner leads are routed in the element-mounting region.   
     
     
         17 . The semiconductor device according to  claim 16 ,
 wherein the first inner leads are arranged on the side of the first outer lead portion, and the second inner leads are routed from the second outer lead portion toward the first outer lead portion via the element-mounting region.   
     
     
         18 . A lead frame, comprising:
 an element-mounting region;   an outer lead portion having a plurality of outer leads;   an inner lead portion having a plurality of inner leads, at least part of the inner leads being routed in the element-mounting region; and   an insulation resin filled into gaps between the inner leads located on at least part of the element-mounting region.   
     
     
         19 . The lead frame according to  claim 18 ,
 wherein the outer lead portion is provided with a first outer lead portion having first outer leads and a second outer lead portion having second outer leads arranged to oppose to the first outer leads with the element-mounting region between them, and the inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads,   wherein at least either the first or second inner leads are routed in the element-mounting region.   
     
     
         20 . The lead frame according to  claim 18 ,
 wherein the outer lead portion is provided with a first outer lead portion having first outer leads and a second outer lead portion having second outer leads arranged to oppose to the first outer leads with the element-mounting region between them, and the inner lead portion has first inner leads connected to the first outer leads, second inner leads connected to the second outer leads, and third inner leads electrically independent of the first and second outer leads,   wherein the first, second and third inner leads are at least partly routed in the element-mounting region.

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