Firmware Update for Storage Device

Abstract

A storage device includes a firmware memory, a buffer memory, a processor and a memory update controller. When the storage device is under a normal mode, the memory update controller is in an idle state. The processor controls the storage device to fetch an update firmware and store the update firmware into the buffer memory. When the storage device is under a firmware update mode, the processor is in an idle state. The memory update controller fetches the update firmware from the buffer memory and stores the update firmware into the firmware memory without the processor executing an update routine code.

1 . A storage device having a normal operation mode and a firmware update mode, the storage device comprising:
 a firmware memory;   a buffer memory;   a processor electrically connected to the firmware memory, for controlling the storage device to fetch an update firmware and store the update firmware into the buffer memory when the storage device is under the normal operation mode; and   a memory update controller electrically connected to the firmware memory and the buffer memory, for fetching the update firmware from the buffer memory and storing the update firmware into the firmware memory when the storage device is under the firmware update mode without the processor executing an update routine code for updating firmware stored in the firmware memory.   
   
   
       2 . The storage device of  claim 1 , wherein the processor controls the storage device to fetch the update firmware from an optical disc. 
   
   
       3 . The storage device of  claim 1 , wherein the memory update controller comprises:
 a direct memory access (DMA) unit electrically connected to the buffer memory, for fetching the update firmware from the buffer memory; and   a dedicated memory update unit electrically connected to the DMA unit and the firmware memory, for receiving the update firmware from the DMA unit and storing the update firmware into the firmware memory.   
   
   
       4 . The storage device of  claim 1 , wherein when the storage device is under the normal operation mode, the processor executes the firmware stored in the firmware memory to control operations of the storage device. 
   
   
       5 . The storage device of  claim 1 , wherein when the storage device is under the firmware update mode, the processor is in an idle state; and when the storage device is under the normal operation mode, the memory update controller is in an idle state. 
   
   
       6 . The storage device of  claim 1 , wherein the processor and the memory update controller are set in a system control chip of the storage device. 
   
   
       7 . The storage device of  claim 1 , wherein the firmware memory is a flash memory, an electrical erasable programmable read only memory (EEPROM), or a serial flash memory. 
   
   
       8 . The storage device of  claim 1 , wherein the buffer memory is a dynamic random access memory (DRAM) or a synchronous dynamic random access memory (SDRAM). 
   
   
       9 . A system control chip utilized in a storage device, for updating firmware of the storage device, the system control chip comprising:
 a processor electrically connected to a firmware memory of the storage device, the firmware memory being for storing firmware of the storage device;   a controller electrically connected to the processor, for receiving a control signal and general data;   a decoder electrically connected to the processor, the controller, and a buffer memory of the storage device; and   a memory update controller electrically connected to the processor and the firmware memory, for receiving an update firmware and storing the update firmware into the firmware memory without the processor executing an update routine code for updating firmware stored in the firmware memory.   
   
   
       10 . The system control chip of  claim 9 , wherein the memory update controller is further electrically connected to the decoder, and receives the update firmware from the decoder. 
   
   
       11 . The system control chip of  claim 10 , wherein the memory update controller comprises:
 a direct memory access (DMA) unit electrically connected to the decoder, for receiving the update firmware from the decoder; and   a dedicated memory update unit electrically connected to the DMA unit and the firmware memory, for receiving the update firmware from the DMA unit and storing the update firmware into the firmware memory.   
   
   
       12 . The system control chip of  claim 9 , wherein the processor, the controller, the decoder, and the memory update controller are interconnected through a data bus. 
   
   
       13 . The system control chip of  claim 12 , wherein the processor sets the memory update controller through the data bus. 
   
   
       14 . The system control chip of  claim 9 , wherein the processor executes the firmware stored in the firmware memory to control operations of the decoder and the controller. 
   
   
       15 . The system control chip of  claim 9 , wherein the firmware memory is a flash memory, an electrical erasable programmable read only memory (EEPROM), or a serial flash memory. 
   
   
       16 . The system control chip of  claim 9 , wherein the buffer memory is a dynamic random access memory (DRAM) or a synchronous dynamic random access memory (SDRAM). 
   
   
       17 . A firmware update method utilized in a storage device, the storage device comprising a firmware memory, a buffer memory, a processor, and a memory update controller, the firmware update method comprising:
 (a) controlling the storage device to fetch an update firmware and store the update firmware into the buffer memory with the processor; and   (b) without utilizing the processor to execute an update routine code for updating firmware stored in the firmware memory, utilizing the memory update controller to fetch the update firmware from the buffer memory and store the update firmware into the firmware memory.   
   
   
       18 . The firmware update method of  claim 17 , wherein step (a) controls the storage device to fetch the update firmware from an optical disc. 
   
   
       19 . The firmware update method of  claim 17 , wherein:
 step (a) further comprises controlling the memory update controller to be in an idle state; and   step (b) further comprises controlling the processor to be in an idle state.   
   
   
       20 . The firmware update method of  claim 17 , wherein the firmware memory is a flash memory, an electrical erasable programmable read only memory (EEPROM), or a serial flash memory. 
   
   
       21 . The firmware update method of  claim 17 , wherein the buffer memory is a dynamic random access memory (DRAM) or a synchronous dynamic random access memory (SDRAM).