Memory Packages Having Stair Step Interconnection Layers

Abstract

Disclosed are IC package structures having stair stepped layers and which have no plated vias. Such structures can be fabricated either as discrete packages or as strips such as might be beneficial in for use with memory devices wherein critical or high speed signals can be routed along the length of the multi-chip strip package without having to have the signals ascend and descend from the interconnection substrate on which the assembly is mounted to the IC package termination and back as the signal transmits between devices.

1 - 10 . (canceled) 
     
     
         11 . An electrical assembly comprising:
 a first IC memory package with a first plurality of memory dies including a first memory die, each memory die having an active surface with a plurality of die terminals disposed thereon, the first memory die having a first die terminal in electrical continuity with first and second die bond-pads formed on the active surface.   
     
     
         12 . The electrical assembly of  claim 11  wherein a surface region of the first die terminal is coextensive with at least part of a surface region of the first die bond-pad. 
     
     
         13 . The electrical assembly of  claim 11  wherein the first die bond-pad and second die-bond pad are electrically coupled, at least in part, by a signal trace. 
     
     
         14 . The electrical assembly of  claim 13  wherein the signal trace is formed on the active surface of the first memory die. 
     
     
         15 . The electrical assembly of  claim 11 , the first IC memory package further comprising:
 a first dielectric layer with an active surface having a first plurality of circuit traces disposed thereupon, including a first circuit trace, the first plurality of circuit traces having first and second terminal ends; and,   a first bond wire with a first end coupled to the first circuit trace and a second end coupled with the first die bond-pad.   
     
     
         16 . The electrical assembly of  claim 15  further comprising a second wire bond coupling the second die bond-pad to a second circuit trace. 
     
     
         17 . The electrical assembly of  claim 16  wherein the first dielectric layer comprises a back surface coupled to the active surfaces of the first plurality of memory dies. 
     
     
         18 . The electrical assembly of  claim 17 , wherein the first dielectric layer comprises a first plurality of apertures configured to expose at least some of the die bond-pads on the active surfaces of the first plurality of memory dies. 
     
     
         19 . The electrical assembly of  claim 18  further comprising a second dielectric layer with an active surface and a back surface, the active surface having a second plurality of circuit traces disposed thereupon, each of the second plurality of circuit traces having first and second ends, wherein the back surface of the second dielectric layer is coupled to the active surface of the first dielectric layer. 
     
     
         20 . The electrical assembly of  claim 19  wherein the second dielectric layer covers at least a portion of some of the first plurality of signal traces, the second dielectric layer comprising a second plurality of apertures configured in a stair step arrangement with at least some of the first plurality of apertures, and wherein the second plurality of apertures are configured to expose the first end of at least some of the first plurality of circuit traces. 
     
     
         21 . The electrical assembly of  claim 20  wherein the second plurality of circuit traces includes the second circuit trace. 
     
     
         22 . The electrical assembly of  claim 20  wherein the first plurality of circuit traces includes the second circuit trace. 
     
     
         23 . The electrical assembly of  claim 11 , wherein the first plurality of memory dies are disposed on a first carrier. 
     
     
         24 . The electrical assembly of  claim 23  wherein the first carrier comprises a plurality of cavities, and wherein the first memory die is disposed in a first cavity, and the second memory die is disposed in a second cavity. 
     
     
         25 . The electrical assembly of  claim 23  wherein an edge of a first memory die in the first IC memory package abuts an edge of a second memory die in the first IC memory package. 
     
     
         26 . The electrical assembly of  claim 11  further comprising:
 a printed circuit board wherein said first IC memory package is mounted on the printed circuit board;   a plurality of edge connector terminals disposed along at least one edge of the printed circuit board;   a second IC memory package mounted on the printed circuit board, wherein the first and second IC memory packages are electrically coupled to the edge connector terminals on the printed circuit board.   
     
     
         27 . The electrical assembly of  claim 26  further comprising:
 an advanced memory buffer mounted on the printed circuit board and electrically coupled to the first and second IC memory packages.   
     
     
         28 . An electrical assembly with a first IC memory package, the first IC memory package comprising:
 a first memory die having an active surface with a plurality of die bond pads disposed thereon, including first and second die bond pads   a first dielectric layer having a back surface disposed against the active surface of the first memory die, and an active surface with a first plurality of circuit traces disposed thereon, including a first circuit trace with first and second terminal ends configured to couple with corresponding conductive members; and,   a first bond wire with a first end coupled to the first die bond pad and a second end coupled to a first section of the first circuit trace between the first and second terminal ends.   
     
     
         29 . The electrical assembly of  claim 28 , wherein the first dielectric layer comprises a first aperture exposing the first die bond pad and a second aperture exposing the second die bond pad, the first and second apertures being separated by a first dielectric bridge, wherein the first circuit trace spans the first dielectric bridge. 
     
     
         30 . The electrical assembly of  claim 29 , wherein the first memory die comprises two parallel rows of die bond pads, including a third die bond pad adjacent the first die bond pad and exposed by the first aperture, and a fourth die bond pad adjacent the second die bond pad and exposed by the second aperture. 
     
     
         31 . The electrical assembly of  claim 30 , wherein the first plurality of circuit traces further comprises a second circuit trace with first and second terminal ends, the first IC memory package further comprising a second bond wire with a first end coupled with the fourth die bond pad and a second end coupled with a first section of the second circuit trace between the first and second terminal ends. 
     
     
         32 . The electrical assembly of  claim 31 , wherein the second circuit trace spans the first dielectric bridge abreast the first circuit trace. 
     
     
         33 . The electrical assembly of  claim 32 , wherein the first dielectric layer further comprises third and fourth apertures separated by a second dielectric bridge, the third and fourth apertures exposing respective third and fourth die bond pads disposed on the active surface of the second memory die. 
     
     
         34 . The electrical assembly of  claim 33 , wherein the first circuit trace further spans the second dielectric bridge. 
     
     
         35 . The electrical assembly of  claim 34 , the first IC memory package further comprising a second bond wire with a first end coupled to the first circuit trace, and a second end coupled to the third die bond pad. 
     
     
         36 . The electrical assembly of  claim 29 , the first IC memory package further comprising:
 a second dielectric layer with a back surface disposed against the active surface of the first dielectric layer, and an active surface that has a second plurality of conductive circuit traces disposed thereon, including a second circuit trace; and,   a second bond wire electrically coupled from the second die bond pad to the second circuit trace.   
     
     
         37 . The electrical assembly of  claim 36 , wherein the second dielectric surface comprises a third aperture disposed above, and in stair step relationship with the first and second apertures. 
     
     
         38 . The electrical assembly of  claim 34 , the first IC memory package further comprising a third memory die with an active surface having a plurality of die bond pads, including a fifth die bond pad electrically coupled to the first circuit trace by a wire bond. 
     
     
         39 . The electrical assembly of  claim 26  wherein the first circuit trace has a first end engaging a first conductive member of a next level electrical component, a second end engaging a second conductive member of a next level electrical component, and wherein the first bond wire is coupled to the first circuit trace between the first and second ends. 
     
     
         40 . The electrical assembly of  claim 39  wherein the first IC memory package is mounted on a memory card having edge connection terminals, the electrical assembly further comprising:
 an advanced memory buffer mounted on the memory card and electrically coupled with the first IC memory package; and,   a second IC memory package mounted on the memory card and electrically coupled with the advanced memory buffer.   
     
     
         41 . An electrical assembly with a first IC memory package, the first IC memory package comprising:
 a plurality of memory dies including first and second memory dies, each memory die having an active surface that has at least three parallel rows of die bond pads, including first and second outer rows, and a third inner row disposed between the outer rows;   a first dielectric layer with an active surface that has a first plurality of circuit traces disposed thereon, including first and second circuit traces, wherein the active surface of the first dielectric layer faces the active surface of the first memory die, and wherein a first die bond terminal in the first outer row is coupled to the first circuit trace by a conductive bump, and a second die bond terminal in the second outer row is coupled to the second circuit trace by a second conductive bump.   
     
     
         42 . The electrical assembly of  claim 41  further comprising a second dielectric layer with a back surface coupled to the first dielectric layer, and an active surface with a second plurality of circuit traces disposed thereon, including a third signal trace. 
     
     
         43 . The electrical assembly of  claim 42  further comprising a bond wire with a first end coupled to a die bond pad in the third row of die bond pads, and a second end coupled to the third signal trace. 
     
     
         44 . The electrical assembly of  claim 41  wherein the plurality of memory dies are disposed on a carrier. 
     
     
         45 . The electrical assembly of  claim 44  wherein the carrier comprises a plurality of cavities, and wherein the first memory die is disposed in a first cavity, and the second memory die is disposed in a second cavity. 
     
     
         46 . The electrical assembly of  claim 44  wherein an edge of a first memory die in the first IC memory package abuts an edge of the second memory die in the first IC memory package. 
     
     
         47 . The electrical assembly of  claim 41  wherein the first IC memory package is mounted on a memory card having edge connection terminals, the electrical assembly further comprising:
 an advanced memory buffer mounted on the memory card and electrically coupled with the first IC memory package; and,   a second IC memory package mounted on the memory card and electrically coupled with the advanced memory buffer.