Method for Manufacturing Semiconductor Device

Abstract

A semiconductor device is provided. The semiconductor device according to the present invention includes a semiconductor substrate, a second insulation layer, a buffer insulation layer adjacent to the second insulation layer, a third insulation layer and transistors. A high voltage device region and a low voltage device region are defined in the semiconductor substrate. The second and third insulation layers are formed in the high and low voltage device regions, respectively. The transistors are formed on the second and third insulation layers, respectively.

1 . A semiconductor device comprising:
 a semiconductor substrate having a high voltage device region and a low voltage device region;   a high voltage insulation layer in the high voltage device region with a buffer insulation layer adjacent thereto;   a low voltage insulation layer in the low voltage device region; and   transistor gate electrodes on the high voltage insulation layer and the low voltage insulation layer.   
   
   
       2 . The semiconductor device according to  claim 1 , wherein the high voltage insulation layer is thicker than the buffer insulation layer and the low voltage insulation layer. 
   
   
       3 . The semiconductor device according to  claim 1 , wherein the high voltage insulation layer comprises a local oxidation of silicon (LOCOS) structure. 
   
   
       4 . The semiconductor device according to  claim 1 , wherein the buffer insulation layer is thicker than the low voltage insulation layer. 
   
   
       5 . The semiconductor device according to  claim 1 , further comprising source and drain regions at lateral sides of the gate electrodes. 
   
   
       6 . The semiconductor device according to  claim 5 , further comprising a salicide layer on the source and drain regions. 
   
   
       7 . The semiconductor device according to  claim 5 , further comprising source and drain electrodes in contact with the respective source and drain regions. 
   
   
       8 . The semiconductor device according to  claim 1 , wherein the high voltage insulation layer has a thickness of about 350˜450 Å. 
   
   
       9 . The semiconductor device according to  claim 1 , wherein the high voltage insulation layer is wider than the corresponding gate electrode on the high voltage insulation layer. 
   
   
       10 . The semiconductor device according to  claim 1 , wherein the buffer insulation layer has a thickness of 100˜200 Å. 
   
   
       11 . The semiconductor device according to  claim 1 , wherein the buffer insulation layer comprises an oxide. 
   
   
       12 . The semiconductor device according to  claim 1 , wherein the high voltage insulation layer and the buffer insulation layer have a thickness ratio of from 7:4 to 9:2. 
   
   
       13 . The semiconductor device according to  claim 1 , wherein the low voltage insulation layer serves as a gate insulation layer in the low voltage device region. 
   
   
       14 . The semiconductor device according to  claim 1 , wherein the transistor gate electrodes comprise polysilicon.